Modeling of charge noise in spin qubits

Thanks to strong partnerships between several research institutes, Grenoble is a pioneer in the development of future technologies based on spin qubits using manufacturing processes identical to those used in the silicon microelectronics industry. The spin of a qubit is often manipulated with alternating electrical (AC) signals through various spin-orbit coupling (SOC) mechanisms that couple it to electric fields. This also makes it sensitive to fluctuations in the qubit's electrical environment, which can lead to large qubit-to-qubit variability and charge noise. The charge noise in the spin qubit devices potentially comes from charging/discharging events within amorphous and defective materials (SiO2, Si3N4, etc.) and device interfaces. The objective of this postdoc is to improve the understanding of charge noise in spin qubit devices through simulations at different scales. This research work will be carried out using an ab initio type method and also through the use of the TB_Sim code, developed within the CEA-IRIG institute. This last one is able of describing very realistic qubit structures using strong atomic and multi-band k.p binding models.

Modeling SiGe based spin qubits

The CEA is developing an original spin qubit platform based on "silicon-on-insulator" (SOI) technology and is now turning to new pathways in Si/SiGe (electrons) and Ge/SiGe (holes). This activity is carried out by a consortium bringing together three of major laboratories in Grenoble: CEA-IRIG, CEA-LETI and CNRS-Néel. On this SOI platform, Grenoble has, for example, demonstrated the electrical manipulation of a single electron spin, as well as the first hole spin qubit, and recently obtained record lifetimes and spin-photon coupling for hole spins. In this context, it is essential to support the development of these advanced quantum technologies with advanced theory and modeling. CEA-IRIG is actively developing TB_Sim code. TB_Sim is able of describing highly realistic qubit structures down to the atomic scale if needed, using atomistic strong bonding models and multi-band k.p models for the electronic structure of materials. Using TB_Sim, CEA has recently examined various aspects of spin qubit physics, in close collaboration with experimental groups in Grenoble and with CEA partners in Europe. The first objective of this research work is to strengthen our understanding of electron spin qubits based on Si/SiGe heterostructures through analytical modeling as well as advanced numerical simulation using TB_Sim. The second objective is to compare the performances of the Si/SiGe platform to other Ge/SiGe and Si MOS platforms to identify its strengths and weaknesses.

Development of innovative metal contacts for 2D-material field-effect-transistors

Further scaling of Si-based devices below 10nm gate length is becoming challenging due to the control of thin channel thickness. For gate length smaller than 10nm, sub-5nm thick Si channel is required. However, the process-induced Si consumption and the reduction of carrier mobility in ultrathin Si layer can limit the channel thickness scaling. Today, the main contenders that allow the extension of the roadmap to ultra-scaled devices are 2D materials, particularly the semiconducting transition metal dichalcogenides (TMD). Due to their unique atomically layered structure, they offer improved immunity to short-channel-effects in comparison to usual Si-based field-effect-transistors (FETs). This makes them very attractive for the application of more-Moore electronics.
However, the scalability of MOSFET device and the introduction of new material make source and drain contact a major issue. If many efforts have been made, in the past years, to reduce Fermi level pinning and Schottky barrier height, for many, these approaches are not industrially scalable. The main objective of this work is then to propose an in-depth understanding of electrical contact characteristics (based on different material) to identify the lowest contact resistance. The processes involved, offering an optimal contact resistance, must be compatible with wafer-scale processing for an integration in our 200/300mm advanced CMOS platform. The post-doc will in-depth study mechanisms enabling the formation of small contact resistances (between MoS2 and metal). It will have to identify the most promising contact material and to develop the associated deposition processes (ALD/PVD). Finally, electrical characterization of contact will be performed to qualify both material and interfaces enabling optimal operation of future 2D FETs

Design of in-memory high-dimensional-computing system

Conventional von Neumann architecture faces many challenges in dealing with data-intensive artificial intelligence tasks efficiently due to huge amounts of data movement between physically separated data computing and storage units. Novel computing-in-memory (CIM) architecture implements data processing and storage in the same place, and thus can be much more energy-efficient than state-of-the-art von Neumann architecture. Compared with their counterparts, resistive random-access memory (RRAM)-based CIM systems could consume much less power and area when processing the same amount of data. This makes RRAM very attractive for both in-memory and neuromorphic computing applications.

In the field of machine learning, convolutional neural networks (CNN) are now widely used for artificial intelligence applications due to their significant performance. Nevertheless, for many tasks, machine learning requires large amounts of data and may be computationally very expensive and time consuming to train, with important issues (overfitting, exploding gradient and class imbalance). Among alternative brain-inspired computing paradigm, high-dimensional computing (HDC), based on random distributed representation, offers a promising way for learning tasks. Unlike conventional computing, HDC computes with (pseudo)-random hypervectors of D-dimension. This implies significant advantages: a simple algorithm with a well-defined set of arithmetic operations, with fast and single-pass learning that can benefit from a memory-centric architecture (highly energy-efficient and fast thanks to a high degree of parallelism).

Design of optomechanical oscillators for cryogenic applications

Quantum computing is seen as a disruptive technology that could pave the way to the design of new computers able to solve problems out of reach of classical architectures. One of the challenges towards quantum computing is to provide solutions of electronics able to control and read the Qubits at cryogenic temperature.
Oscillators is a key function of cryogenic temperature that can be found in the qbit readout electronics or in the various reference frequency generators needed for high data-rate transmissions for example. The postdoc will consist in designing low phase, low power and low volume oscillator using an innovative optomechanical resonator under study in LETI and to study its performances at cryogenic temperature. The post doc will take advantage of already existing devices at LICA laboratory and on the experience of LGECA laboratory on the design of optomechanical conditioning circuits and on the characterization of cryogenic circuits.

Design of Ising Machines based on a network of spintronics oscillators copled through CMOS circuitry

Our information and communication society is asking for always more computing tasks of increasing complexity. Their energy bargain increases quickly so that it is mandatory to find new architecture of computing processors with improved energy efficiency.
The post doc applicant will contribute to the design of Ising machines which are computing architectures inspired from biology and physics and which permit to solve complex optimization problems. Under the scope of SpinIM project (french ANR funding), the applicant will contribute to the demonstration of an Ising machine based on the electrical coupling of spin torque nano-oscillators (STNO). More specifically, the post doc role will be to design the configurable CMOS chip implementing the electrical coupling. He will have to propose a VerilogA model of the STNO with the help of Spintec experience on STNO theory. Then the post doc will have to propose an optimized design of the CMOS chip from schematics to layout and he will have to assess the chip performances in laboratory. Finally, the post doc will participate to the demonstration of the full Ising machine consisting of the CMOS chip and a STNO network on some optimization tasks. The post doc will take place in the LGECA laboratory of CEA-Leti which have gained experience on CMOS-Spintronics co-design.

Design and fabrication of the magnetic control of 1.000 qubits arrays

Quantum computing is nowadays a strong field of research at CEA-LETI and in numerous institutes and companies around the world. In particular, RF magnetic fields allow to control the spin of silicon qubits, and pathway for large scale control is a real technological challenge.
The bibliographic analysis and the studies already carried out will able to draw out the pros and cons of the various existing solutions. In collaboration with integration, simulation and design staff, a proof of concept will be develloped and fabricated.

Development of large area substrates for power electronics

Improving the performance of power electronics components is a major challenge for reducing our energy consumption. Diamond appears as the ultimate candidate for power electronics. However, the small dimensions and the price of the substrates are obstacles to the use of this material. The main objective of the work is to overcome these two difficulties by slicing the samples into thin layers by SmartCut™ and by tiling these thin layers to obtain substrates compatible with microelectronics.
For this, various experiments will be carried out in a clean room. Firstly, the SmartCut™ process must be made more reliable. Characterizations such as optical microscopy, AFM, SEM, Raman, XPS, electrical, etc. will be carried out in order to better understand the mechanisms involved in this process.
The candidate might be required to work on other wide-gap materials studied in the laboratory such as GaN and SiC, which will allow him to have a broader view of substrates for power electronics.

Design of 2D Matrix For Silicum Quantum computing with Validation by Simulation

The objective is to design a 2D matrix structure for quantum computing on silicon in order to consider structures of several hundred physical Qubits.

In particular the subject will be focused on:
- The functionality of the structure (Coulomb interaction, RF and quantum)
- Manufacturing constraints (simulation and realistic process constraint)
- The variability of the components (Taking into account the variability parameter and realistic defectivity)
- The constraints induced on the algorithms (error correction code)
- Scalability of the structure to thousands of physical Qubits

The candidate will work within a project of more than fifty people with expertise covering the design, fabrication, characterization and modeling of spin qubits as well as related disciplines (cryoelectronics, quantum algorithms, quantum error correction, …)

Effect of TSV presence on BEOL reliability for 3-layer stacked CMOS image sensor (CIS)

Because conventional downsizing based on the empirical Moore's law has reached its limitations, an alternative integration technology, such as three-dimensional integration (3DI) is becoming the mainstream. The 3rd generation of CMOS image sensor (CIS) stacks up to 3 die interconnected by hybrid bonding and High Density Through Silicon Vias (HD-TSVs). Devices and circuits good functioning and integrity have to be maintained in such an integration especially in the close neighborhood of TSVs. Thermal budget, copper pumping, thin wafer warpage can lead to electrical yield and reliability concerns and must be investigated.
The work consists in evaluating the impact of TSV processing and proximity on BEOL and FEOL performance and reliability. Acquired data sets will help to define design rules and in particular a potential Keep-Out Zone (KOZ) and calibrate a finite element model (FFM).