DTCO for RF & mmW Applications:Focus on Homogeneous & Heterogeneous Chiplet Hybrid Bonding Challenge
In recent years, there have been numerous technological advancements in silicon-based semiconductors. However, the limits in terms of frequency performance and power seem to have been reached, requiring the development of new type III-V devices (such as InP and GaN) that are faster, more powerful and well adapted for new RF mmW applications. For reasons of flexibility, performance, and cost, it is crucial to co-integrate these new high-performance III-V components with the more traditional silicon technologies. This is one of the major objectives of the proposed topic.
The focus will be on the design and optimisation of millimetre-wave RF circuits using 3D heterogeneous hybrid bonding assembly technology. In recent years, numerous test vehicles have been fabricated and characterised to demonstrate the advantages and disadvantages of the hybrid bonding assembly process for millimetre wave RF applications. The aim is to extend this work and focus the studies and research on real RF systems, such as millimetre-wave power amplifiers. The DTCO (Design and Technology Co-Optimisations) approach will not only enable the design of efficient 3D RF circuits, but will also allow the adaptation of different 3D design rules to make 3D hybrid bonding technology relevant for the production of millimetre-scale 3D integrated systems.
2D materials electrical characterization for microelectronics
Future microelectronic components will be ever smaller and ever more energy-efficient. To meet this challenge, 2D materials are excellent candidates, thanks to their remarkable dimensions and electronic properties (high mobility of charge carriers, high light emission/absorption). What's more, they feature van der Waals (vdW) surfaces, i.e. no dangling bonds, enabling them to retain their properties even at very small dimensions (down to the monolayer). New 2D materials and vdW stacks with novel physical properties are being discovered every day. However, integrating them and measuring their performance in circuits remains an ongoing challenge, as their properties must be preserved during integration.
The aim of this post-doc is to develop components for qualifying 2D materials for microelectronic (RF transistor) and spintronic (magnetic memory) applications in horizontal configuration on silicon. A vertical measurement method has already been developed by CEA LETI. Building on these developments, the candidate will develop this measurement system and characterize various materials produced in MBE by CEA-IRIG. The work will involve transferring these layers onto chips, optimizing the electrical contacts and developing the in-plane electrical measurement chain.
Comparison of Diamond and vertical GaN technologies to SiC and Si for power applications
Power devices based on wide band gap semiconductors are increasingly being studied and adopted in commercial products, driven by the electrification of our societies. Among these wide band gap devices, SiC-based technologies are the most mature, at the industrial production stage. Other materials are being studied to achieve higher performance, in particular diamond, whose intrinsic physical properties offer great potential, as well as GaN components in a vertical architecture. However, the real benefits of these materials compared with existing Si or SiC solutions have not been clearly demonstrated and might strongly depend on the applications considered. The aim of this project is to identify one or more applications where vertical GaN and diamond technologies are likely to bring significant benefits, taking into account the current and/or projected market for these applications. Then, using TCAD and SPICE simulations as well as experimental test device characterizations, we will compare the estimated performance of industrially viable diamond and GaN components, designed for these applications, with that of SiC and Si.
Disruptive RF substrates based on polycrystalline materials
A high resistivity substrate is essential for the design of state-of-the-art high-frequency circuits. The high-resistivity (HR) SOI substrate with a trap-rich layer below the buried oxide (BOX) is the option with the highest performance at present for CMOS technologies. However, these substrates have two major limitations: (1) their relatively high price and (2) the degradation of their RF performance at operating temperatures above 100 °C.
As part of this postdoctoral study, we propose to study, in collaboration with the Catholic University of Louvain (UCL), the RF performance over a wide temperature range of a polycrystalline substrate over its entire thickness (several hundred µm). These polycrystalline substrates indeed have a high density of electronic traps distributed throughout the entire volume, which in principle allows for stable RF performance even at high operating temperatures.
The person hired will participate in the following research: (1) screening of promising substrates from TCAD simulations (e.g. poly-Si, poly-SiC, …), (2) integration of polycrystalline substrates in an SOI process flow at Leti, (3) measurement of RF performances in frequency and temperature at UCL. A particular attention will be placed on understanding the physical phenomena involved through the comparison of experimental and simulation data.
High-performance computing using CMOS technology at cryogenic temperature
Advances in materials, transistor architectures, and lithography technologies have enabled exponential growth in the performance and energy efficiency of integrated circuits. New research directions, including operation at cryogenic temperatures, could lead to further progress. Cryogenic electronics, essential for manipulating qubits at very low temperatures, is rapidly developing. Processors operating at 4.2 K using 1.4 zJ per operation have been proposed, based on superconducting electronics. Another approach involves creating very fast sequential processors using specific technologies and low temperatures, reducing energy dissipation but requiring cooling. At low temperatures, the performance of advanced CMOS transistors increases, allowing operation at lower voltages and higher operating frequencies. This could improve the sequential efficiency of computers and simplify the parallelization of software code. However, materials and component architectures need to be rethought to maximize the benefits of low temperatures. The post-doctoral project aims to determine whether cryogenic temperatures offer sufficient performance gains for CMOS or should be viewed as a catalyst for new high-performance computing technologies. The goal is particularly to assess the increase in processing speed with conventional silicon components at low temperatures, integrating measurements and simulations.
Simulation of thermal transport at sub-Kelvin
Thermal management in quantum computers is an urgent and crucial task. As the number of qubits rapidly scales, more electric circuits are placed close to qubits to operate them. Joule-heating of these circuits could significantly warm the qubit device, degrading its fidelity. With intensive activity in quantum computing at Grenoble, we (CEA-LETI, Grenoble, France) are looking for an enthusiastic post-doc researcher to study thermal transport at cryogenic temperature (sub-Kelvin).
The post-doc will apply the finite-element non-equilibrium Green’s function [1], developed in the group of Natalio Mingo at CEA-Grenoble, to simulate phonon transport in various designed structures. The simulation result promotes comparison with on-going experiments and constructive discussions in order to optimize the thermal management.
[1] C. A. Polanco, A. van Roekeghem, B. Brisuda, L. Saminadayar, O. Bourgeois, and N. Mingo, Science Advances 9, 7439 (2023).
Modeling of charge noise in spin qubits
Thanks to strong partnerships between several research institutes, Grenoble is a pioneer in the development of future technologies based on spin qubits using manufacturing processes identical to those used in the silicon microelectronics industry. The spin of a qubit is often manipulated with alternating electrical (AC) signals through various spin-orbit coupling (SOC) mechanisms that couple it to electric fields. This also makes it sensitive to fluctuations in the qubit's electrical environment, which can lead to large qubit-to-qubit variability and charge noise. The charge noise in the spin qubit devices potentially comes from charging/discharging events within amorphous and defective materials (SiO2, Si3N4, etc.) and device interfaces. The objective of this postdoc is to improve the understanding of charge noise in spin qubit devices through simulations at different scales. This research work will be carried out using an ab initio type method and also through the use of the TB_Sim code, developed within the CEA-IRIG institute. This last one is able of describing very realistic qubit structures using strong atomic and multi-band k.p binding models.
Design and fabrication of the magnetic control of 1.000 qubits arrays
Quantum computing is nowadays a strong field of research at CEA-LETI and in numerous institutes and companies around the world. In particular, RF magnetic fields allow to control the spin of silicon qubits, and pathway for large scale control is a real technological challenge.
The bibliographic analysis and the studies already carried out will able to draw out the pros and cons of the various existing solutions. In collaboration with integration, simulation and design staff, a proof of concept will be develloped and fabricated.
Development of large area substrates for power electronics
Improving the performance of power electronics components is a major challenge for reducing our energy consumption. Diamond appears as the ultimate candidate for power electronics. However, the small dimensions and the price of the substrates are obstacles to the use of this material. The main objective of the work is to overcome these two difficulties by slicing the samples into thin layers by SmartCut™ and by tiling these thin layers to obtain substrates compatible with microelectronics.
For this, various experiments will be carried out in a clean room. Firstly, the SmartCut™ process must be made more reliable. Characterizations such as optical microscopy, AFM, SEM, Raman, XPS, electrical, etc. will be carried out in order to better understand the mechanisms involved in this process.
The candidate might be required to work on other wide-gap materials studied in the laboratory such as GaN and SiC, which will allow him to have a broader view of substrates for power electronics.
Design of 2D Matrix For Silicum Quantum computing with Validation by Simulation
The objective is to design a 2D matrix structure for quantum computing on silicon in order to consider structures of several hundred physical Qubits.
In particular the subject will be focused on:
- The functionality of the structure (Coulomb interaction, RF and quantum)
- Manufacturing constraints (simulation and realistic process constraint)
- The variability of the components (Taking into account the variability parameter and realistic defectivity)
- The constraints induced on the algorithms (error correction code)
- Scalability of the structure to thousands of physical Qubits
The candidate will work within a project of more than fifty people with expertise covering the design, fabrication, characterization and modeling of spin qubits as well as related disciplines (cryoelectronics, quantum algorithms, quantum error correction, …)