Modeling of trapping and vertical leakage effects in GaN epitaxial substrates on Si
State of the art: Understanding and modeling vertical leakage currents and trapping effects in GaN substrates on Si are among the crucial subjects of studies aimed at improving the properties of GaN power components : current collapse and Vth instabilities reductions, reduction of the leakage current in the OFF state.
Many universities [Longobardi et al. ISPSD 2017 / Uren et al. IEEE TED 2018 / Lu et al. IEEE TED 2018] and industrials [Moens et al. ISPSD 2017] are trying to model vertical leakages but until now, no clear mechanism has emerged from this work to model them correctly over the entire range of voltage and temperatures targeted. In addition, modeling the effects of traps in the epitaxy is necessary for the establishment of a a robust and predictive TCAD model of device.
For LETI, the strategic interest of such a work is twofold: 1) Understanding and reducing the effects of traps in the epitaxy impacting the functioning of GaN devices on Si (current collapse, Vth instabilities…) 2) Reaching the leakage specifications @ 650V necessary for industrial applications.
The candidate will have to take charge in parallel of the electrical characterizations and the development of TCAD models:
A) Advanced electrical characterizations (I (V), I (t), substrate ramping, C (V)) as a function of temperature and illumination on epitaxial substrates or directly on finite components (HEMT, Diodes, TLM )
B) Establishment of a robust TCAD model integrating the different layers of the epitaxy in order to understand the effects of device instabilities (dynamic Vth, dynamic Ron, BTI)
C) Modeling of vertical conduction in epitaxy with the aim of reducing leakage currents at 650V
Finally, the candidate must be proactive in improving the different parts of the substrate
Digital circuit design for In-Memory Computing in advanced Resistive-RAM NVM technology
For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
CEA-Leti launched a project on this topic, leveraging three key enabling technologies, under development at CEA-Leti: non-volatile resistive memory (RRAM), new energy-efficient nanowire transistors and 3D-monolithic integration [ArXiv 2012.00061]. A 3D In-Memory-Computing accelerator circuit will be designed, manufactured and measured, targeting a 20x reduction in (Energy x Delay) Product vs. Von-Neumann systems.
Simulation and electrical characterization of an innovative logic/memory CUBE for In-Memory-Computing
For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items. Things will change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. At LETI, we will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory.
The post-doc will perform electrical characterizations of CMOS transistors and Resistive RAMs in order to calibrate models and run TCAD/spice simulations to drive the technology developments and enable the circuit designs.
FDSOI technology scaling beyond 10nm node
FDSOI (Fully-Depleted Silicon On Insulator) is acknowledged as a promising technology to meet the requirements of emerging mobile, Internet Of Things (IOT), and RF applications for scaled technological nodes [1]. Leti is a pioneer in FDSOI technology, enabling innovative solutions to support industrial partners.
Scaling of FDSOI technology beyond 10nm node offers solid perspectives in terms of SoC and RF technologies improvement. Though from a technological point of view, it becomes challenging because of thin channel thickness scaling limitation around 5nm to maintain both good mobility and variability. Thus, introduction of innovative technological boosters such as strain modules, alternative gate process, parasitics optimization, according to design rules and applications, become mandatory [2].
The viability of these new concepts should be validated first by TCAD simulations and then implemented on our 300mm FDSOI platform.
This subject is in line with the recent LETI strategy announcement and investments to develop new technological prototypes for innovative technology beyond 28nm [3].
The candidate will be in charge to perform TCAD simulations, to define experiment and to manage them until the electrical characterization. The TCAD simulations will be performed in close collaboration with the TCAD team. The integration will be done in the LETI clean room in collaboration with the process and integration team. Candidate with out-of-the-BOX thinking, autonomy, and ability to work in team is mandatory.
[1] 22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications, R. Carter et al, IEEE IEDM 2016.
[2] UTBB FDSOI scaling enablers for the 10nm node, L. Grenouillet et al, IEEE S3S 2013.
[3]https://www.usinenouvelle.com/article/le-leti-investit-120-millions-d-euros-dans-sa-salle-blanche-pour-preparer-les-prochaines-innovations-dans-les-puces.
AlGaN/GaN HEMTs transfert for enhanced electrical and thermal performances
Due to their large critical electric field and high electron mobility, gallium nitride (GaN) based devices emerge as credible candidates for power electronic applications. In order to face the large market needs and benefit from available silicon manufacturing facilities, the current trend is to fabricate those devices, such as aluminum gallium nitride (AlGaN)/GaN high electron mobility transistors (HEMTs), directly on (111) silicon substrates. However, this pursuit of economic sustainability negatively affects device performances mainly because of self-heating effect inherent to silicon substrate use. New substrates with better thermal properties than silicon are desirable to improve thermal dissipation and enlarge the operating range at high performance.
A Ph.D. student in the lab. has developed a method to replace the original silicon material with copper, starting from AlGaN/GaN HEMTs fabricated on silicon substrates. He has demonstrated the interest of the postponement of a GaN power HEMT on a copper metal base with respect to self heating without degrading the voltage resistance of the component. But there are still many points to study to improve the power components.
Post-doc objectives : We propose to understand what is the best integration to eliminate self-heating and increase the voltage resistance of the initial AlGaN/GaN HEMT. The impact of the component transfer on the quality of the 2D gas will be analyzed.
The same approach can be made if necessary on RF components.
Different stacks will be made by the post-doc and he will be in charge of the electrical and thermal characterizations. Understanding the role of each part of the structure will be critical in choosing the final stack.
This process will also be brought in larger dimensions.
This post-doc will work if necessary in collaboration with different thesis students on power components.
Simulation of semimetal nanowires
The candidate’s mission will be:
• Simulation using ab-initio tools of the structure of bismuth nanowire bands of different diameters (from 1 nm to 10 nm).
• Extraction of parameters as effective masses, density of states, band offsets for these nanowires.
• Implementation of these parameters in a NEGF simulator to simulate bismuth nanowire transistors with variable diameter.
• Ab-initio simulation of the bismuth-dielectric nanowire interface and study of various elements of chemical passivation.
• This work will be done in collaboration with LETI / DCOS / SCME / LSIM (Philippe Blaise)
• The candidate will interact with an experimental team that will produce the simulated devices and will help to supervise one or more doctoral students, in collaboration with IMEP.
• The candidate will interact with the LTM to help predict the properties of the grid bismuth-insulator interface and implement the IMEP results in the simulator.
Development of lead free piezoelectric actuator
At CEA-Tech, the LETI Institute creates innovation and transfers it to industry. The micro-actuator component laboratory (LCMA) is working on the integration of piezoelectric materials into microsystems that allow electromechanical transduction. Lead zirconate titanate (PZT) is today the most powerful piezoelectric material for micro-actuator applications. However, the introduction in the near future of a new standard regarding the lead amount allowed in chips (European RoHS directive) leads us to evaluate alternative lead-free materials to PZT for piezoelectric actuator applications. The development of lead-free materials has thus become a major focus of piezoelectric research. This research led to revisit and modify some classical piezoelectric such as KNbO3 and BaTiO3. In particular, the KNaxNb1-xO3 (KNN) family has been identified as promising. The objective of the postdoc is therefore to evaluate some lead-free piezoelectric materials and to compare their properties with that of the reference material, PZT. Suitable test vehicles will be fabricated in LETI’s clean rooms for electrical and piezoelectric characterizations by mean of dedicated tools already available at lab. For this work the candidate will lean on a solid experience developed at LETI for more than 20 years on piezoelectric thin films.
Bio-compatible, bio-resorbable microbatteries for medical applications
In the framework of its activities dedicated to embedded micro-batteries, LETI initiates prospective research in the field of micro-batteries for medical applications, and in particular as energy power sources for implantable micro-devices. In this context, a collaborative project, including LETI labs and an academic Partner (ICMCB, Bordeaux), is aiming at designing, manufacturing and studying prototypes of bio-resorbable primary microbatteries.
The main tasks will include (i) a contribution to the design of the thin film electrochemical cell by the selection of adequate biocompatible materials (able to generate the targeted electrical power, corrodible and able to solubilize in the body), (ii) the manufacture of the cell constituents (electrodes, electrolyte, substrate) as thin films (sputtering, electrochemical plating, doctor blade coating) and their characterization,(iii) the achievement of full prototype cells and the study of their in vitro behaviour.
The work will be carried out at ICMCB (Bordeaux) in a joint CEA/ICMCB team, in collaboration with LETI labs in Grenoble.
Optimisation of the monolithic cascode device based on GaN/Si MOS-Channel HEMT technology
In order to adress the requirements of power conversion in the field of electrical vehicule or photovoltaics, high performance GaN on Silicon power devices need to be developped. Such power devices must fulfill agressive specifications in terms of threshold voltage (> 2V), nominal current (100-200A), breakdown voltage (650 and 1200V) and stability (low "current collapse", low hysteresis). Discrete cascode configuration, consisting in a combination of a low voltage E-mode Silicon die and a hihg voltage D-mode GaN/Si die in a single package, has been developped by different laboratories and companies to adress this need (Transphorm, On-Semi, NXP, IR…). However, this approach has some drawbacks like parasitic inductances, device pairing, need of additionnal protection devices, cost, temperature limitation due to the Si die...
The monolithic cascode is a very compact version of the cascode configuration that will allow to avoid those problems but also to improve the performance of E-mode devices developped at Leti (MOS-channel HEMT). Indeed, some actors in the field of GaN power devices already use this configuration with another E-mode technology (p-GaN gate).
Monolithic cascode device has been demonstrated recently by CEA-Leti in the frame of a PhD thesis (2014-2016) on the basis of the 200mm GaN/Si, CMOS compatible, MOS-channel HEMT technology. The aim of this post-doc is to optimize the monolithic cascode structure in terms of On-state resistance, Figure Of Merit, switching losses and high switching frequency capability in order to meet the specifications of our industrial partners.
Frequency tunable elastic plate wave resonators and filters
The increasing number of frequency bands having to be dealt with in mobile phone systems require a huge number of band pass filters in such systems. In this context, the capability to provide frequency tunable resonators and filters is seen as a key enabling element in future wireless transmission systems.
CEA-LETI has been working for more than 10 years on the development of resonators and filters exploiting the propagation of guided elastic waves in piezoelectric thin films. It has also proposed several concepts for frequency agile resonators and filters.
The purpose of this post-doc will be to further develop these ideas and to apply them to the design of demonstrators matching realistic specifications. In collaboration with the other member of the project team, more focused on fabrication in clean rooms, the candidate will propose innovative structures demonstrating frequency tuning of reconfigurability, and will take in charge their electrical characterization.