Effect of TSV presence on BEOL reliability for 3-layer stacked CMOS image sensor (CIS)
Because conventional downsizing based on the empirical Moore's law has reached its limitations, an alternative integration technology, such as three-dimensional integration (3DI) is becoming the mainstream. The 3rd generation of CMOS image sensor (CIS) stacks up to 3 die interconnected by hybrid bonding and High Density Through Silicon Vias (HD-TSVs). Devices and circuits good functioning and integrity have to be maintained in such an integration especially in the close neighborhood of TSVs. Thermal budget, copper pumping, thin wafer warpage can lead to electrical yield and reliability concerns and must be investigated.
The work consists in evaluating the impact of TSV processing and proximity on BEOL and FEOL performance and reliability. Acquired data sets will help to define design rules and in particular a potential Keep-Out Zone (KOZ) and calibrate a finite element model (FFM).
Optomechanical force probes development for high speed AFM
The proposed topic is part of a CARNOT project aiming at developing a new generation of force sensors based on optomechanical transduction. These force sensors will be implemented in ultrafast AFM microscopes for imaging and force spectroscopy. They will allow to address biological and biomedical applications on sub-microsecond or even nanosecond time scales in force spectroscopy mode.
First optomechanical VLSI force probes on silicon have been designed and fabricated in LETI's industrial grade clean rooms and have led to first proofs of concept for fast AFM [1,2]. The post-doctoral student will be in charge of the preparation of force probes in order to integrate them in a high speed AFM developed by our partner at CNRS LAAS (Toulouse). He will be in charge of the back end operations, from the release of the structures, their observation (SEM, optical microscopies, etc.), to the optical packaging with fiber optic ferrules. He will also participate in the development of a test bench for components before and after packaging to select devices and validate the packaged probes before integration into an AFM.
The post-doctoral student will also investigate the operation of the probe in a liquid medium to allow later AFM studies of biological phenomena: for this, the development of efficient actuation means (electrostatic, thermal or optical) of the mechanical structure will be carried out and applied experimentally. A feedback on the modeling and the design is expected from the measurements, in order to ensure the understanding of the observed physical phenomena. Finally, the post-doctoral fellow will have the possibility to propose new device designs to target the expected performances. The devices will be fabricated in Leti's clean room, then tested and compared to the expected performances.
Multi-scale modeling of the electromagnetic quantum dot environment
In the near future, emerging quantum information technologies are expected to lead to global breakthroughs in high performance computing and secure communication. Among semiconductor approaches, silicon-based spin quantum bits (qubits) are promising thanks to their compactness featuring long coherence time, high fidelity and fast qubit rotation [Maurand2016], [Meunier2019]. A main challenge is now to achieve individual qubit control inside qubit arrays.
Qubit array constitutes a compact open system, where each qubit cannot be considered as isolated since it depends on the neighboring qubit placement, their interconnection network and the back-end-line stack. The main goal of this post-doctoral position is to develop various implementation of spin control on 2D qubit array using multi-scale electromagnetic (EM) simulation ranging from nanometric single qubit up to millimetric interconnect network.
The candidate will i) characterize radio-frequency (RF) test structures at cryogenic temperature using state-of-the-art equipment and compare results with dedicated EM simulations, ii) evaluate the efficiency of spin control and allow multi-scale optimization from single to qubit arrays [Niquet2020], iii) integrate RF spin microwave control for 2D qubit array using CEA-LETI silicon technologies.
The candidate need to have a good RF and microelectronic background and experience in EM simulation, and/or design of RF test structures and RF characterization. This work takes place in a dynamic tripartite collaborative project between CEA-LETI, CEA-IRIG and CNRS-Institut Néel (ERC “Qucube”).
Hybrid CMOS / spintronic circuits for Ising machines
The proposed research project is related to the search for hardware accelerators for solving NP-hard optimization problems. Such problems, for which finding exact solutions in polynomial time is out of reach for deterministic Turing machines, find many applications in diverse fields such as logistic operations, circuit design, medical diagnosis, Smart Grid management etc.
One approach in particular is derived from the Ising model, and is based on the evolution (and convergence) of a set of binary states within an artificial neural network (ANN).In order to improve the convergence speed and accuracy, the network elements may benefit from an intrinsic and adjustable source of fluctuations. Recent proof-of-concept work highlights the interest of implementing such neurons with stochastic magnetic tunnel junctions (MTJ).
The main goals will be the simulation, dimensioning and fabrication of hybrid CMOS/MTJ elements. The test vehicles will then be characterized in order to validate their functionality.
This work will be carried out in the frame of a scientific collaboration between CEA-Leti and Spintec.
Modeling of trapping and vertical leakage effects in GaN epitaxial substrates on Si
State of the art: Understanding and modeling vertical leakage currents and trapping effects in GaN substrates on Si are among the crucial subjects of studies aimed at improving the properties of GaN power components : current collapse and Vth instabilities reductions, reduction of the leakage current in the OFF state.
Many universities [Longobardi et al. ISPSD 2017 / Uren et al. IEEE TED 2018 / Lu et al. IEEE TED 2018] and industrials [Moens et al. ISPSD 2017] are trying to model vertical leakages but until now, no clear mechanism has emerged from this work to model them correctly over the entire range of voltage and temperatures targeted. In addition, modeling the effects of traps in the epitaxy is necessary for the establishment of a a robust and predictive TCAD model of device.
For LETI, the strategic interest of such a work is twofold: 1) Understanding and reducing the effects of traps in the epitaxy impacting the functioning of GaN devices on Si (current collapse, Vth instabilities…) 2) Reaching the leakage specifications @ 650V necessary for industrial applications.
The candidate will have to take charge in parallel of the electrical characterizations and the development of TCAD models:
A) Advanced electrical characterizations (I (V), I (t), substrate ramping, C (V)) as a function of temperature and illumination on epitaxial substrates or directly on finite components (HEMT, Diodes, TLM )
B) Establishment of a robust TCAD model integrating the different layers of the epitaxy in order to understand the effects of device instabilities (dynamic Vth, dynamic Ron, BTI)
C) Modeling of vertical conduction in epitaxy with the aim of reducing leakage currents at 650V
Finally, the candidate must be proactive in improving the different parts of the substrate
Digital circuit design for In-Memory Computing in advanced Resistive-RAM NVM technology
For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
CEA-Leti launched a project on this topic, leveraging three key enabling technologies, under development at CEA-Leti: non-volatile resistive memory (RRAM), new energy-efficient nanowire transistors and 3D-monolithic integration [ArXiv 2012.00061]. A 3D In-Memory-Computing accelerator circuit will be designed, manufactured and measured, targeting a 20x reduction in (Energy x Delay) Product vs. Von-Neumann systems.
Simulation and electrical characterization of an innovative logic/memory CUBE for In-Memory-Computing
For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items. Things will change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. At LETI, we will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory.
The post-doc will perform electrical characterizations of CMOS transistors and Resistive RAMs in order to calibrate models and run TCAD/spice simulations to drive the technology developments and enable the circuit designs.
FDSOI technology scaling beyond 10nm node
FDSOI (Fully-Depleted Silicon On Insulator) is acknowledged as a promising technology to meet the requirements of emerging mobile, Internet Of Things (IOT), and RF applications for scaled technological nodes [1]. Leti is a pioneer in FDSOI technology, enabling innovative solutions to support industrial partners.
Scaling of FDSOI technology beyond 10nm node offers solid perspectives in terms of SoC and RF technologies improvement. Though from a technological point of view, it becomes challenging because of thin channel thickness scaling limitation around 5nm to maintain both good mobility and variability. Thus, introduction of innovative technological boosters such as strain modules, alternative gate process, parasitics optimization, according to design rules and applications, become mandatory [2].
The viability of these new concepts should be validated first by TCAD simulations and then implemented on our 300mm FDSOI platform.
This subject is in line with the recent LETI strategy announcement and investments to develop new technological prototypes for innovative technology beyond 28nm [3].
The candidate will be in charge to perform TCAD simulations, to define experiment and to manage them until the electrical characterization. The TCAD simulations will be performed in close collaboration with the TCAD team. The integration will be done in the LETI clean room in collaboration with the process and integration team. Candidate with out-of-the-BOX thinking, autonomy, and ability to work in team is mandatory.
[1] 22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications, R. Carter et al, IEEE IEDM 2016.
[2] UTBB FDSOI scaling enablers for the 10nm node, L. Grenouillet et al, IEEE S3S 2013.
[3]https://www.usinenouvelle.com/article/le-leti-investit-120-millions-d-euros-dans-sa-salle-blanche-pour-preparer-les-prochaines-innovations-dans-les-puces.
AlGaN/GaN HEMTs transfert for enhanced electrical and thermal performances
Due to their large critical electric field and high electron mobility, gallium nitride (GaN) based devices emerge as credible candidates for power electronic applications. In order to face the large market needs and benefit from available silicon manufacturing facilities, the current trend is to fabricate those devices, such as aluminum gallium nitride (AlGaN)/GaN high electron mobility transistors (HEMTs), directly on (111) silicon substrates. However, this pursuit of economic sustainability negatively affects device performances mainly because of self-heating effect inherent to silicon substrate use. New substrates with better thermal properties than silicon are desirable to improve thermal dissipation and enlarge the operating range at high performance.
A Ph.D. student in the lab. has developed a method to replace the original silicon material with copper, starting from AlGaN/GaN HEMTs fabricated on silicon substrates. He has demonstrated the interest of the postponement of a GaN power HEMT on a copper metal base with respect to self heating without degrading the voltage resistance of the component. But there are still many points to study to improve the power components.
Post-doc objectives : We propose to understand what is the best integration to eliminate self-heating and increase the voltage resistance of the initial AlGaN/GaN HEMT. The impact of the component transfer on the quality of the 2D gas will be analyzed.
The same approach can be made if necessary on RF components.
Different stacks will be made by the post-doc and he will be in charge of the electrical and thermal characterizations. Understanding the role of each part of the structure will be critical in choosing the final stack.
This process will also be brought in larger dimensions.
This post-doc will work if necessary in collaboration with different thesis students on power components.
Simulation of semimetal nanowires
The candidate’s mission will be:
• Simulation using ab-initio tools of the structure of bismuth nanowire bands of different diameters (from 1 nm to 10 nm).
• Extraction of parameters as effective masses, density of states, band offsets for these nanowires.
• Implementation of these parameters in a NEGF simulator to simulate bismuth nanowire transistors with variable diameter.
• Ab-initio simulation of the bismuth-dielectric nanowire interface and study of various elements of chemical passivation.
• This work will be done in collaboration with LETI / DCOS / SCME / LSIM (Philippe Blaise)
• The candidate will interact with an experimental team that will produce the simulated devices and will help to supervise one or more doctoral students, in collaboration with IMEP.
• The candidate will interact with the LTM to help predict the properties of the grid bismuth-insulator interface and implement the IMEP results in the simulator.