In order to adress the requirements of power conversion in the field of electrical vehicule or photovoltaics, high performance GaN on Silicon power devices need to be developped. Such power devices must fulfill agressive specifications in terms of threshold voltage (> 2V), nominal current (100-200A), breakdown voltage (650 and 1200V) and stability (low "current collapse", low hysteresis). Discrete cascode configuration, consisting in a combination of a low voltage E-mode Silicon die and a hihg voltage D-mode GaN/Si die in a single package, has been developped by different laboratories and companies to adress this need (Transphorm, On-Semi, NXP, IR…). However, this approach has some drawbacks like parasitic inductances, device pairing, need of additionnal protection devices, cost, temperature limitation due to the Si die...
The monolithic cascode is a very compact version of the cascode configuration that will allow to avoid those problems but also to improve the performance of E-mode devices developped at Leti (MOS-channel HEMT). Indeed, some actors in the field of GaN power devices already use this configuration with another E-mode technology (p-GaN gate).
Monolithic cascode device has been demonstrated recently by CEA-Leti in the frame of a PhD thesis (2014-2016) on the basis of the 200mm GaN/Si, CMOS compatible, MOS-channel HEMT technology. The aim of this post-doc is to optimize the monolithic cascode structure in terms of On-state resistance, Figure Of Merit, switching losses and high switching frequency capability in order to meet the specifications of our industrial partners.

The post-DOC will support the device modeling part of a research project investigating new methodologies for system and circuit optimization with the aim of achieving a better integration between the knowledge of the detailed characteristics of a specific technology, the circuit-design methodology and the system architecture. The practical goal is to leverage the existing multi-disciplinary know-how for benchmarking of system and technologies to advance the analysis past the usual PPA, PPAY and PPAC approaches that are commonly deployed in such cases.
In more detail, the post-DOC will develop "pre"-spice models for actives and passives which will constitute the basic bricks for the optimization methodology developed in the overall project. Active device modeling will have a starting point in the works of EPFL based on the analytical expression of invariants such has the inversion coefficient.

Transition Metal Dicalchogenides (TMDs) have displayed interesting properties in numerous fields of nanotechnoogy (CMOS, memory, sensors, photonics etc.), and emerge as promising materials thanks to their functional properties and potential for co-integration, facilitated by their intrinsic features (van der Waals materials). However, their applicative impact remains uncertain due to the challenge of developing their processing in a standard nanoelectronics environment while maintaining a good control of their fundamental properties. The candidate will quantify the electrical properties of various 2D materials in test structures derived from a silicon technology baseline (TLM, Cross-Bridge Kelvin Résistors, MOS capacitors), in order to provide guidelines for device prototyping.

Specifically, the primary aim is to assess the interest of these materials as interface layers rather than for transport, for improving:
- The contact resistivity via Fermi-level depinning.
- Control by the Gate over the inversion charge in the channel via a negative differential capacitance effect.

In this postdoc, we propose to investigate Resistive memories (RRAM) as a Storage Class Memory (SCM) for high density memory applications. To this aim, both CBRAM and OXRAM will be studied and compared. RRAM technologies, integrating various resistive layers, top and bottom electrodes will be integrated.
Then electrical characterization will be performed on these different memory options. The impact of the integration flow on the memory characteristics will be addressed, to evaluate how critical integration steps may impact the memory operation. In particular, MESA (the RRAM stack is etched) vs Damascene (the RRAM stack is deposited in a cavity) approaches will be compared.
After the evaluation of the memory basic operation (forming, SET and RESET operation speed, required voltages…), a specific focus will be made on reliability. In particular, endurance will be deeply investigated and optimized. The impact of SET RESET conditions (including smart programming schemes) on the window margin and number of cycles will be analyzed. Finally, the variability issue will be highly covered, in order to quantify how cycle to cycle and device to device variability close the window margin of the RRAM. Specific reliability concerns (read noise…) will also be addressed. Extrapolations on the maximum density a given RRAM technology can reach will be drawn.
Based on this detailed study, a benchmark of all the tested RRAM technologies will be made, to identify the pros and cons of each option, and highlight the tradeoff that have to be found (among them: memory speed, endurance, operating voltages, consumption…).