Development of an hermetic thin flim packaging for RF MEMS switches
Leti has developed for many years a RF MEMS switch process which have demonstrated RF performances at the state-of-the-art as well as a process maturity level closed to industrial standards. To finalize its component and especially to ensure long-terms reliability level for space applications, Leti is today developing an innovative hermetic thin film packaging process.
The applicant will join a project team working on the development of this new technological brick. In a first step, the applicant will be in charge of the design of the process test vehicles, of the follow-up of their silicon batches fabrication in clean room and of their characterization during the process. In a second step, the applicant will perform a modeling study to optimize the design of the switches integrating this new packaging. In particular, he will propose new designs for mid RF power applications. Finally, the applicant will be in charge of the follow-up of the realization of silicon batches for the RF MEMS switches demonstrators. He will then supervise and participate to all the characterization studies on packaged components.
Design of a new generation of MEMS flow or viscosity sensors
This Post-doc is defined to answer to various industrial requests for flow sensors and viscosity sensors working on a large range, low cost and able to measure different kind of fluids (liquid or gas).
The objective of this post-doc is to consider the design of a new generation of MEMS sensor for measuring flow or viscosity of any fluid that meets the specifications provided by the industry.
In particular, the possibilities of using a 3-axis micro-force sensor developed in the laboratory will be explored by exploiting the drag force or the tangential stresses near the walls of the pipes. Different cases will have to be evaluated depending on the flow dynamics of the different fluids.
A modeling and sizing of the sensor will have to be developed to determine the interactions with the fluids and the characteristics of the forces in the different flow rates.
The candidate should possess strong knowledge on fluidic and microsystems.
Development of innovative metal contacts for 2D-material field-effect-transistors
Further scaling of Si-based devices below 10nm gate length is becoming challenging due to the control of thin channel thickness. For gate length smaller than 10nm, sub-5nm thick Si channel is required. However, the process-induced Si consumption and the reduction of carrier mobility in ultrathin Si layer can limit the channel thickness scaling. Today, the main contenders that allow the extension of the roadmap to ultra-scaled devices are 2D materials, particularly the semiconducting transition metal dichalcogenides (TMD). Due to their unique atomically layered structure, they offer improved immunity to short-channel-effects in comparison to usual Si-based field-effect-transistors (FETs). This makes them very attractive for the application of more-Moore electronics.
However, the scalability of MOSFET device and the introduction of new material make source and drain contact a major issue. If many efforts have been made, in the past years, to reduce Fermi level pinning and Schottky barrier height, for many, these approaches are not industrially scalable. The main objective of this work is then to propose an in-depth understanding of electrical contact characteristics (based on different material) to identify the lowest contact resistance. The processes involved, offering an optimal contact resistance, must be compatible with wafer-scale processing for an integration in our 200/300mm advanced CMOS platform. The post-doc will in-depth study mechanisms enabling the formation of small contact resistances (between MoS2 and metal). It will have to identify the most promising contact material and to develop the associated deposition processes (ALD/PVD). Finally, electrical characterization of contact will be performed to qualify both material and interfaces enabling optimal operation of future 2D FETs
Reliability of the copper (Cu) direct bonding interconnects for 3D integration
Copper direct bonding is one of the most promising approaches for 3-D integration. The process is mature as shown in the literrature for wafer to wafer (W2W) approach [1-3] but also in the case of a die to wafer one (D2W). However, its reliability is yet to be demonstrated even if the initial results from the PhD thesis of R. Taibi seem to be promising [4].
The purpose of this post-doc position will be first, to consolidate the results obtained by R. Taibi with the W2W approach and secondly, to study the reliability of the D2W approach from the electromigration and stress-induced voiding point of view.
The candidate will be responsible for all the reliability study, starting with the tests and the results’ analysis, failure analysis (optical, IR, SEM, FIB...), the determination of the degradation’s mechanisms.
1. Gueguen, P., et al. Copper direct bonding for 3D integration. in Interconnect Technology Conference, 2008. IITC 2008. International. 2008.
2. Taibi, R., et al. Full characterization of Cu/Cu direct bonding for 3D integration. in Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th. 2010.
3. Di Cioccio, L., et al., An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization. Journal of The Electrochemical Society, 2011. 158(6): p. 81-86.
4. Taibi, R., et al., Investigation of Stress Induced Voiding and Electromigration Phenomena on Direct Copper Bonding Interconnects for 3D Integration, in 2011 IEEE International Electron Devices Meeting (IEDM). 2011: Washington, DC.
Electrical Study of Conductive Bridge Random access Memory (CBRAM)
CBRAM memories are among the most promising technologies as alternative to Flash technologies which face strong problems of scaling. CBRAM have a capacitor-like stack, where a chalcogenide material is sandwiched between a silver anode and an inert cathode. Biasing the cell, silver ions diffuse in the chalcogenide matrix and reach the cathode where they reduce. A conductive bridge is formed between the electrodes causing a drop of resistance. Reversing the bias yields to a back-migration of silver, interrupting the conductive bridge. This kind of device can be operated at very low voltage (below 1 V) and can lead to extremely low power consumption.
The main objective of this postdoc position will be the electrical characterization aiming to a better comprehension of the physics involved in the device, with the final goal of a strong improvement in device characteristics, in particular concerning data retention. For this aim, in-depth characterization on particular features (i.e. conduction mode, failure mechanisms) will be performed, as much as possible linked to a first level of physical modelling linking current conduction and diffused ions in the matrix. The candidate will address both hardware & methodology issues, and particular attention will be devoted to pulsed measurements. Various process, geometries and architectures will be studied. A strong interaction with the specialists of materials characterizations (nano-characterization platform) will be promoted for a better physical knowledge of the structures.
Study of the thermo-mechanical strains in the HEMT AlGaN/GaN on silicon
Fabricating the HEMT AlGaN/GaN device is complex and leads to the formation of crystalline defects. These strains, in the GaN layer, leads to crackings in the GaN layer or leads to a delamination at the top interface. Moreover, these mechanical strains conjugated to thermal strains during device working, can lead to a degradation of the electrical performance of the device.
This heterogeneous assembly, involve a complex behaviour. The various materials used, react differently to the thermal-mechanical strains. The requested work is to study and to model the distortion of this structure, in order to evaluate the strains effects on the electrical performance on lateral and vertical devices.
Design of in-memory high-dimensional-computing system
Conventional von Neumann architecture faces many challenges in dealing with data-intensive artificial intelligence tasks efficiently due to huge amounts of data movement between physically separated data computing and storage units. Novel computing-in-memory (CIM) architecture implements data processing and storage in the same place, and thus can be much more energy-efficient than state-of-the-art von Neumann architecture. Compared with their counterparts, resistive random-access memory (RRAM)-based CIM systems could consume much less power and area when processing the same amount of data. This makes RRAM very attractive for both in-memory and neuromorphic computing applications.
In the field of machine learning, convolutional neural networks (CNN) are now widely used for artificial intelligence applications due to their significant performance. Nevertheless, for many tasks, machine learning requires large amounts of data and may be computationally very expensive and time consuming to train, with important issues (overfitting, exploding gradient and class imbalance). Among alternative brain-inspired computing paradigm, high-dimensional computing (HDC), based on random distributed representation, offers a promising way for learning tasks. Unlike conventional computing, HDC computes with (pseudo)-random hypervectors of D-dimension. This implies significant advantages: a simple algorithm with a well-defined set of arithmetic operations, with fast and single-pass learning that can benefit from a memory-centric architecture (highly energy-efficient and fast thanks to a high degree of parallelism).
Quantum dot auto-tuning assisted by physics-informed neural networks
Quantum computers hold great promise for advancing science, technology, and society by solving problems beyond classical computers' capabilities. One of the most promising quantum bit (qubit) technologies are spin qubits, based on quantum dots (QDs) that leverage the great maturity and scalability of semiconductor technologies. However, scaling up the number of spin qubits requires overcoming significant engineering challenges, such as the charge tuning of a very large number of QDs. The QD tuning process implies multiple complex steps that are currently performed manually by experimentalists, which is cumbersome and time consuming. It is now crucial to address this problem in order to both accelerate R&D and enable truly scalable quantum computers.
The main goal of the postdoctoral project is to develop a QD automatic tuning software combining Bayesian neural networks and a QD physical model fitted on CEA-Leti’s device behavior. This innovative approach leveraging the BayNN uncertainty estimations and the predictive aspect of QD models will enable to achieve fast and non-ideality-resilient automatic QD tuning solutions.
DTCO analysis of MRAM for In/Near-Memory Computing
The energy cost associated to moving data across the memory hierarchy has become a limiting factor in modern computing systems. To mitigate this trend, novel computing architectures favoring a more local and parallel processing of the stored information are proposed, under the labels « Near/In-Memory Computing » or « Processing In Memory ». Substantial benefits are expected in particular for computationally complex (e.g. combinatorial optimization, graph analysis, cryptography) and data-intensive tasks (e.g. video stream analysis, bio-informatics). Such applications are especially demanding in terms of endurance, latency and density. SRAM, fulfilling the first two criteria, may eventually suffer from its footprint and static power consumption. This prompts the evaluation of alternative denser and non-volatile memory technologies, with magnetoresistive memories (MRAM) currently leading in terms of speed-endurance trade-off.
The primary objective will be to estimate improvements brought by MRAM in terms of array-level power, performance, area (PPA), as compared to SRAM-based on-chip memories and for advanced technology nodes. The candidate will establish an analysis and benchmarking workflow for various classes of MRAM, and optimize single bit cells based on a compact model for the memory element. This baseline approach will then be adapted to functional variations specific to IMC in order to assess the benefits of MRAM on an integrated test vehicle.
Design of Ising Machines based on a network of spintronics oscillators copled through CMOS circuitry
Our information and communication society is asking for always more computing tasks of increasing complexity. Their energy bargain increases quickly so that it is mandatory to find new architecture of computing processors with improved energy efficiency.
The post doc applicant will contribute to the design of Ising machines which are computing architectures inspired from biology and physics and which permit to solve complex optimization problems. Under the scope of SpinIM project (french ANR funding), the applicant will contribute to the demonstration of an Ising machine based on the electrical coupling of spin torque nano-oscillators (STNO). More specifically, the post doc role will be to design the configurable CMOS chip implementing the electrical coupling. He will have to propose a VerilogA model of the STNO with the help of Spintec experience on STNO theory. Then the post doc will have to propose an optimized design of the CMOS chip from schematics to layout and he will have to assess the chip performances in laboratory. Finally, the post doc will participate to the demonstration of the full Ising machine consisting of the CMOS chip and a STNO network on some optimization tasks. The post doc will take place in the LGECA laboratory of CEA-Leti which have gained experience on CMOS-Spintronics co-design.