Low temperature process modules for 3d coolcube integration : through the end of roadmap

3D sequential integration is envisaged as a possible solution until the end of CMOS roadmap. Different process modules have been developped @ 500°C for planar FDSOI technology in a gate first process. However, regarding bottom transistor level stability in CoolcubeTM integration, and yield consideration, the need to reduce further the top transistor temperature down to 450°C should be explored.
The post-doc will have in charge the development of specific technological modules at low temperature both 500°C and 450°C for FDSOI planar devices to acquire a solid knowledge in low temperature CMOS process integration. The specific low temperature gate module will be addressed on planar devices. The threshold voltage modulation will also be studied.
The work will be performed in collaboration with the technological platform process of LETI for the low temperature modules development. The electrical characterization in collaboration with the characterization laboratory and the TCAD simulations team of LETI.

Electrical Characterization of resistive memory devices

The activity of the postdoc will be focused on electrical characterization and physical modeling of devices with integrated bistable oxides (ie NiO, HfO2): mainly he will address both the hardware & methodology to address the non-volatile memory performances (ie write/erase, data retention and endurance), and he will perform measurements on several devices featuring different bistable oxides (ie NiO, HfO2…). Note that particular attention will be devoted to pulsed measurements tailored for “non-polar” or “bipolar” devices. After having collected sufficient ensemble of data on memory performance, he will try to interpret them in the simplest form with possibly semi-analitycal models in order to catch the basics of physics relying behind the electrical data.