The energy cost associated to moving data across the memory hierarchy has become a limiting factor in modern computing systems. To mitigate this trend, novel computing architectures favoring a more local and parallel processing of the stored information are proposed, under the labels « Near/In-Memory Computing » or « Processing In Memory ». Substantial benefits are expected in particular for computationally complex (e.g. combinatorial optimization, graph analysis, cryptography) and data-intensive tasks (e.g. video stream analysis, bio-informatics). Such applications are especially demanding in terms of endurance, latency and density. SRAM, fulfilling the first two criteria, may eventually suffer from its footprint and static power consumption. This prompts the evaluation of alternative denser and non-volatile memory technologies, with magnetoresistive memories (MRAM) currently leading in terms of speed-endurance trade-off.

The primary objective will be to estimate improvements brought by MRAM in terms of array-level power, performance, area (PPA), as compared to SRAM-based on-chip memories and for advanced technology nodes. The candidate will establish an analysis and benchmarking workflow for various classes of MRAM, and optimize single bit cells based on a compact model for the memory element. This baseline approach will then be adapted to functional variations specific to IMC in order to assess the benefits of MRAM on an integrated test vehicle.

Our information and communication society is asking for always more computing tasks of increasing complexity. Their energy bargain increases quickly so that it is mandatory to find new architecture of computing processors with improved energy efficiency.
The post doc applicant will contribute to the design of Ising machines which are computing architectures inspired from biology and physics and which permit to solve complex optimization problems. Under the scope of SpinIM project (french ANR funding), the applicant will contribute to the demonstration of an Ising machine based on the electrical coupling of spin torque nano-oscillators (STNO). More specifically, the post doc role will be to design the configurable CMOS chip implementing the electrical coupling. He will have to propose a VerilogA model of the STNO with the help of Spintec experience on STNO theory. Then the post doc will have to propose an optimized design of the CMOS chip from schematics to layout and he will have to assess the chip performances in laboratory. Finally, the post doc will participate to the demonstration of the full Ising machine consisting of the CMOS chip and a STNO network on some optimization tasks. The post doc will take place in the LGECA laboratory of CEA-Leti which have gained experience on CMOS-Spintronics co-design.