GPU ray tracing with OptiX for a Monte Carlo particle transport software
This postdoctoral research subject is proposed in the context of the development by CEA List of the CIVA software platform, used for the simulation of non-destructive testing techniques, in particular X-radiography and computed tomography. This research is supported by a collaborative project between two CEA divisions (DRT and DES). It aims to optimize the performance of the Monte-Carlo method used in the CIVA software in order to improve the processing of complex industrial radiographic configurations. More precisely, More precisely, the following two tasks will be carried out:
- Developing a eTLE-fd type estimator on CPU in the CIVA environment, in order to accelerate the Monte-Carlo calculation by generating pseudo-particles transported directly to the detector. This estimator, already implemented in a DES code (TRIPOLI-4®), will have to be adapted to the NDT applications processed by CIVA.
- Port this estimator to GPU using Nvidia's OptiX library in order to optimize the Monte-Carlo calculation, including taking into account particle attenuation and energy deposition, to be coded in CUDA.
Verification methodology for synchronous systems software
The Synchrone plug-in of Frama-C is dedicated to Lustre programs analysis. It combines the capabilities of the WP and Eva plug-ins and interacts with the GaTeL solver to prove different properties about analyzed programs. This postdoc aims at improving the whole usage of Synchrone throught the following scientific challenges:
- develop a verification methodology that relies on the combination of technics available in the tool, by applying it to representative use-cases,
- in order to support this methodoogy, improve the tools available in Synchrone, in particular the generation of the proof obligations, and their optimization for automatic solvers, like the Colibri2 solver which is developed in the lab,
- improve the link between what the tool verifies and the mathematical specification of the system, by extending LustreSpec and developping associated tools, it comprises aspects related to numerical filters,
- development of tools for visualizing and debugging proof obligations.
This postdoc thus aims at having a global view of the Synchrone tool, targeting publications about proof methodology in an industrial context.
DTCO for RF & mmW Applications:Focus on Homogeneous & Heterogeneous Chiplet Hybrid Bonding Challenge
In recent years, there have been numerous technological advancements in silicon-based semiconductors. However, the limits in terms of frequency performance and power seem to have been reached, requiring the development of new type III-V devices (such as InP and GaN) that are faster, more powerful and well adapted for new RF mmW applications. For reasons of flexibility, performance, and cost, it is crucial to co-integrate these new high-performance III-V components with the more traditional silicon technologies. This is one of the major objectives of the proposed topic.
The focus will be on the design and optimisation of millimetre-wave RF circuits using 3D heterogeneous hybrid bonding assembly technology. In recent years, numerous test vehicles have been fabricated and characterised to demonstrate the advantages and disadvantages of the hybrid bonding assembly process for millimetre wave RF applications. The aim is to extend this work and focus the studies and research on real RF systems, such as millimetre-wave power amplifiers. The DTCO (Design and Technology Co-Optimisations) approach will not only enable the design of efficient 3D RF circuits, but will also allow the adaptation of different 3D design rules to make 3D hybrid bonding technology relevant for the production of millimetre-scale 3D integrated systems.
2D materials electrical characterization for microelectronics
Future microelectronic components will be ever smaller and ever more energy-efficient. To meet this challenge, 2D materials are excellent candidates, thanks to their remarkable dimensions and electronic properties (high mobility of charge carriers, high light emission/absorption). What's more, they feature van der Waals (vdW) surfaces, i.e. no dangling bonds, enabling them to retain their properties even at very small dimensions (down to the monolayer). New 2D materials and vdW stacks with novel physical properties are being discovered every day. However, integrating them and measuring their performance in circuits remains an ongoing challenge, as their properties must be preserved during integration.
The aim of this post-doc is to develop components for qualifying 2D materials for microelectronic (RF transistor) and spintronic (magnetic memory) applications in horizontal configuration on silicon. A vertical measurement method has already been developed by CEA LETI. Building on these developments, the candidate will develop this measurement system and characterize various materials produced in MBE by CEA-IRIG. The work will involve transferring these layers onto chips, optimizing the electrical contacts and developing the in-plane electrical measurement chain.
Comparison of Diamond and vertical GaN technologies to SiC and Si for power applications
Power devices based on wide band gap semiconductors are increasingly being studied and adopted in commercial products, driven by the electrification of our societies. Among these wide band gap devices, SiC-based technologies are the most mature, at the industrial production stage. Other materials are being studied to achieve higher performance, in particular diamond, whose intrinsic physical properties offer great potential, as well as GaN components in a vertical architecture. However, the real benefits of these materials compared with existing Si or SiC solutions have not been clearly demonstrated and might strongly depend on the applications considered. The aim of this project is to identify one or more applications where vertical GaN and diamond technologies are likely to bring significant benefits, taking into account the current and/or projected market for these applications. Then, using TCAD and SPICE simulations as well as experimental test device characterizations, we will compare the estimated performance of industrially viable diamond and GaN components, designed for these applications, with that of SiC and Si.
Disruptive RF substrates based on polycrystalline materials
A high resistivity substrate is essential for the design of state-of-the-art high-frequency circuits. The high-resistivity (HR) SOI substrate with a trap-rich layer below the buried oxide (BOX) is the option with the highest performance at present for CMOS technologies. However, these substrates have two major limitations: (1) their relatively high price and (2) the degradation of their RF performance at operating temperatures above 100 °C.
As part of this postdoctoral study, we propose to study, in collaboration with the Catholic University of Louvain (UCL), the RF performance over a wide temperature range of a polycrystalline substrate over its entire thickness (several hundred µm). These polycrystalline substrates indeed have a high density of electronic traps distributed throughout the entire volume, which in principle allows for stable RF performance even at high operating temperatures.
The person hired will participate in the following research: (1) screening of promising substrates from TCAD simulations (e.g. poly-Si, poly-SiC, …), (2) integration of polycrystalline substrates in an SOI process flow at Leti, (3) measurement of RF performances in frequency and temperature at UCL. A particular attention will be placed on understanding the physical phenomena involved through the comparison of experimental and simulation data.
High-performance computing using CMOS technology at cryogenic temperature
Advances in materials, transistor architectures, and lithography technologies have enabled exponential growth in the performance and energy efficiency of integrated circuits. New research directions, including operation at cryogenic temperatures, could lead to further progress. Cryogenic electronics, essential for manipulating qubits at very low temperatures, is rapidly developing. Processors operating at 4.2 K using 1.4 zJ per operation have been proposed, based on superconducting electronics. Another approach involves creating very fast sequential processors using specific technologies and low temperatures, reducing energy dissipation but requiring cooling. At low temperatures, the performance of advanced CMOS transistors increases, allowing operation at lower voltages and higher operating frequencies. This could improve the sequential efficiency of computers and simplify the parallelization of software code. However, materials and component architectures need to be rethought to maximize the benefits of low temperatures. The post-doctoral project aims to determine whether cryogenic temperatures offer sufficient performance gains for CMOS or should be viewed as a catalyst for new high-performance computing technologies. The goal is particularly to assess the increase in processing speed with conventional silicon components at low temperatures, integrating measurements and simulations.
Design and Implementation of a Neural Network for Thermo-Mechanical Simulation in Additive Manufacturing
The WAAM (Wire Arc Additive Manufacturing) process is a metal additive manufacturing method that allows for the production of large parts with a high deposition rate. However, this process results in highly stressed and deformed parts, making it complex to predict their geometric and mechanical characteristics. Thermomechanical modeling is crucial for predicting these deformations, but it requires significant computational resources and long calculation times. The NEUROWAAM project aims to develop a precise and fast thermomechanical numerical model using neural networks to predict the physical phenomena of the WAAM process. An internship in 2025 will provide a database through thermomechanical simulations using the CAST3M software. The post-doc's objective is to develop a neural network architecture capable of learning the relationship between the manufacturing configuration and the thermomechanical characteristics of the parts. Manufacturing tests on the CEA's PRISMA platform will be conducted to validate the model and prepare a feedback loop. The CEA List's Interactive Simulation Laboratory will contribute its expertise in accelerating simulations through neural networks and active learning to reduce training time.
Digital correction of the health status of an electrical network
Cable faults are generally detected when communication is interrupted, resulting in significant repair costs and downtime. Additionally, data integrity becomes a major concern due to the increased threats of attacks and intrusions on electrical networks, which can disrupt communication. Being able to distinguish between disruptions caused by the degradation of the physical layer of an electrical network and an ongoing attack on the energy network will help guide decision-making regarding corrective operations, particularly network reconfiguration and predictive maintenance, to ensure network resilience. This study proposes to investigate the relationship between incipient faults in cables and their impact on data integrity in the context of Power Line Communication (PLC). The work will be based on deploying instrumentation using electrical reflectometry, combining distributed sensors and AI algorithms for online diagnosis of incipient faults in electrical networks. In the presence of certain faults, advanced AI methods will be applied to correct the state of the health of the electrical network's physical layer, thereby ensuring its reliability.
Advanced reconstruction methods for cryo-electron tomography of biological samples
Cryo-electron tomography (CET) is a powerful technique for the 3D structural analysis of biological samples in their near-native state. CET has seen remarkable advances in instrumentation in the last decade but the classical weighted back-projection (WBP) remains by far the standard CET reconstruction method. Due to radiation damage and the limited tilt range within the microscope, WBP reconstructions suffer from low contrast and elongation artifacts, known as ‘missing wedge’ (MW) artifacts. Recently, there has been a revival of interest in iterative approaches to improve the quality and hence the interpretability of the CET data.
In this project, we propose to go beyond the state-of-the-art in CET by (1) applying curvelet- and shearlet-based compressed sensing (CS) algorithms, and (2) exploring deep learning (DL) strategies with the aim to denoise et correct for the MW artifacts. These approaches have the potential to improve the resolution of the CET reconstructions and facilitate the segmentation and sub-tomogram averaging tasks.
The candidate will conduct a comparative study of iterative algorithms used in life science, and CS and DL approaches optimized in this project for thin curved structures.