Integrated material–process–device co-optimization for the design of high-performance RF transistors on advanced nanometer technologies
This PhD research focuses on the integrated co-optimization of materials, fabrication processes and device architectures to enable high-performance RF transistors on advanced nanometer-scale technologies. The work aims to understand and improve key RF figures of merit—such as transit frequency, maximum oscillation frequency, noise behaviour and linearity—by establishing clear links between material choices, process innovations and transistor design.
The project combines experimental development, structural and electrical characterization, and advanced TCAD simulations to analyse the strengths and limitations of different integration schemes, including FD-SOI and emerging 3D architectures such as GAA and CFET. Particular attention will be given to the engineering of optimized spacers, gate stacks, junction placement and epitaxial source/drain materials in order to minimize parasitic effects and enhance RF efficiency.
By comparing planar and 3D device platforms within a unified modelling and characterization framework, the thesis aims to provide technology guidelines for future generations of energy-efficient RF transistors targeting applications in 5G/6G communications, automotive radar and low-power IoT systems.
Understanding the origin of charge noise in quantum devices
Thanks to strong collaborations between teams from several research institutes and the cleanroom facilities at CEA-LETI, Grenoble has been a pioneer in the development of spin qubit devices as a platform for quantum computing. The lifetime of these spin qubits is highly sensitive to fluctuations in the qubit's electrical environment, known as charge noise. Charge noise in spin qubit devices potentially originates from trapping/detrapping events within the amorphous and defective materials (e.g., SiO2, Si3N4). This PhD project aims to better understand the origin of this noise through numerical simulations, and guide the development of quantum devices towards lower noise levels and higher quality qubits.
The goal of this PhD position is to improve the understanding of noise in spin qubit devices through multi-scale simulations going from the atomistic to the device level. The PhD candidate will use codes developed at CEA for the numerical modeling of spin qubits and will leverage supercomputing facilities to perform the simulations. Depending on the candidate’s profile and interests, code development may be considered. The work will also involve collaborations with experimentalists to validate simulation methods and to aid in the interpretation of experimental results.
Injection-Locked Oscillators based Liquid Neural Networks for Generative Edge Intelligence
This PhD aims to design analog liquid neural networks for generative edge intelligence. Current neuromorphic architectures, although more efficient through in-memory computing, remain limited by their extreme parameter density and interconnection complexity, making their hardware implementation costly and difficult to scale. The Liquid Neural Networks (LNN), introduced by MIT at the algorithmic level, represent a breakthrough: continuous-time dynamic neurons capable of adjusting their internal time constants according to the input signal, thereby drastically reducing the number of required parameters.
The goal of this PhD is to translate LNN algorithms into circuit-level implementations, by developing ultra-low power time-mode cells based on oscillators that reproduce liquid dynamics, and interconnecting them into a stable, recurrent architecture to target generative AI tasks. A silicon demonstrator will be designed and validated, paving the way for a new generation of liquid neuromorphic systems for Edge AI.
Modeling and characterization of CFET transistors for enhanced electrical performance
Complementary Field Effect Transistors (CFETs) represent a new generation of vertically stacked CMOS devices, offering a promising path to continue transistor miniaturization and to meet the requirements of high-performance computing.
The objective of this PhD work is to study and optimize the strain engineering of the transistor channel in order to enhance carrier mobility and improve the overall electrical performance of CFET devices. The work will combine numerical modeling of technological processes using finite element methods with experimental characterization of crystalline deformation through transmission electron microscopy coupled with precession electron diffraction (TEM-PED).
The modeling activity will focus on predicting strain distributions and their impact on electrical properties, while accurately accounting for the complexity of the technological stacks and critical fabrication steps such as epitaxy. In parallel, the experimental work will aim to quantify strain fields using TEM-PED and to compare these results with simulation outputs.
This research will contribute to the development of dedicated modeling tools and advanced characterization methodologies adapted to CFET architectures, with the goal of improving spatial resolution, measurement reproducibility, and the overall understanding of strain mechanisms in next-generation transistors.
Investigation and Modeling of Ferroelectric and Antiferroelectric Domain Dynamics in HfO2-Based Capacitors
The proposed PhD work lies within the exploration of new supercapacitor and hybrid energy storage technologies, aiming to combine miniaturization, high power density, and CMOS process compatibility. The hosting laboratory (LTEI/DCOS/LCRE) has recognized expertise in thin-film integration and dielectric material engineering, offering unique opportunities to investigate ferroelectric (FE) and antiferroelectric (AFE) behaviors in doped hafnium oxide (HfO2).
The thesis will focus on the experimental investigation and physical modeling of thin-film HfO2-based capacitors, intentionally doped to exhibit ferroelectric or antiferroelectric properties depending on the composition and deposition conditions (for instance, through ZrO2 or SiO2 doping). Such materials are particularly attractive for realizing devices that combine non-volatile memory and energy storage functions on a single CMOS-compatible platform, enabling ultra-low-power autonomous systems such as edge computing architectures, environmental sensors, and smart connected objects.
The research will involve the fabrication and characterization of metal–insulator–metal (MIM) capacitors based on doped HfO2 integrated on silicon substrates. Systematic electrical measurements—including current–voltage (I–V) and polarization–electric field (P–E) characterizations—will be carried out under various frequencies, amplitudes, and cycling conditions to investigate the relaxation mechanisms of FE and AFE domains. Analysis of minor hysteresis loops will provide access to the distribution of activation energies and enable the modeling of domain relaxation dynamics. A physical model will be developed or refined to describe FE/AFE transitions under cyclic electrical excitation, incorporating effects such as charge trapping, mechanical stress, and domain nucleation kinetics.
The overall objective is to optimize the recoverable energy density and the energy conversion efficiency of these capacitors, while establishing design guidelines for compact, efficient, and silicon-integrable energy storage devices. The insights gained from this work will contribute to a deeper understanding of the dynamic mechanisms governing FE/AFE behavior in doped HfO2, with potential impact on ferroelectric memories, energy-harvesting devices, and low-power neuromorphic architectures.
Bayesian Neural Inference Using Ferroelectric Memory Transistors
An increasing number of safety-critical systems now rely on artificial intelligence functions that must operate under strict energy constraints and in environments characterized by data scarcity and high uncertainty. However, conventional deterministic AI approaches provide only point estimates and lack principled uncertainty quantification, which can lead to unreliable or unsafe decisions in real-world deployment.
This PhD is positioned within the emerging field of Bayesian electronics, which aims to implement probabilistic inference directly in hardware by leveraging the intrinsic stochasticity of nanoscale devices to represent and manipulate probability distributions. While memristive devices have previously been explored for Bayesian inference, their limited endurance and high programming energy remain critical bottlenecks for on-chip learning.
The objective of this thesis is to investigate ferroelectric field-effect memory transistors (FeMFETs) as building blocks for hardware Bayesian neural networks. The work will involve characterizing and modeling the exploitable ferroelectric randomness for sampling and probabilistic weight updates, designing Bayesian neuron and synapse architectures based on FeMFETs, and evaluating their robustness, energy efficiency, and system-level performance for safety-critical inference under uncertainty.