3D assembly of GaN power devices

The increase in electrical power density in everyday uses is the result of technological developments including materials and components. The first element to address is the use of a semiconductor material suitable for strong integration and capable of managing high power densities. Since the 2010s, wide bandgap semiconductors such as SiC or GaN have emerged in several applications and are causing a revolution in power electronics design, notably with an increase in the operating frequency and specific power of converters. Concerning Galium nitride (GaN), the increase in switching frequency was made possible thanks to the HEMT (High Electron Mobility Transistor).
The idea of ??this PhD topic is to work on a HEMT GaN cell assembly. The work will involve the an assembly of two components through a common electrode on their backsides in order, making it possible to reduce parasitic inductances and increase the operating frequency. The work will be based on simulation tools such as COMSOL and Synopsys. The thesis will be in collaboration with the GEEPS laboratory at CentraleSupelec and the University of Paris-Saclay.

Advanced fully-depleted Silicon-on-insulator devices for Radio-Frequency applications

The PhD will be performed in the NEXTGEN project aimed at developing the next generation of Silicon-on-insulator devices. Our laboratory is driving the development of the RF active devices: this is a great opportunity to carry out fundamental research using state-of-the art processing equipment and characterization instruments while working in close collaboration with our industrial partners.

you will expected to engage in tasks encompassing:
- perform back-of the-envelope estimation of device properties and assess performace impact of technological choices
- Perform and/or analyze TCAD simulations to gain insight in the RF device behaviour
- data-mining on engineering measurements: grasp the relevant information and identify trends or correlations
- perform extensive periods of time in the lab to conduct or participate in on-wafer RF characterization champaign.
Based on you profile or expectations, above tasks may be dynamically rebalanced during the thesis.

Development and characterization of low temperature Cu-dielectric hybrid bonding

Cu-dielectric hybrid bonding is a technology that enables the assembly of components with very fine interconnection pitch, opening the path to new integrations for advanced applications such as High Performance Computing, Smart Imagers,… Leti has been engaged for more than 10 years in the development of this technology, in partnership with various industries and academies, to master smaller and smaller connection pitches (< 1µm), or to evaluate new techniques such as ‘die-to-wafer’ self-assembly. In this context, low temperature hybrid bonding would allow new integration routes notably for heterogeneous systems (III-V on CMOS,…) or for thermally sensitive components (colored resins, non-volatile memories,…).

The objective of this thesis is to develop and characterize Cu-dielectric hybrid assemblies performed at low temperature, from ambient to 250°C. A first part of the thesis will aim at identifying the dielectric materials that are relevant for the hybrid bonding technology (SiN, SiON, SiCN, …). The critical properties of these materials (permittivity, hygroscopy,…) will be measured and compared to the reference high temperature SiO2. In a second part, the selected dielectrics will be integrated in the ‘wafer-to-wafer’ hybrid bonding technology and each process step (damascene level, surface preparation, direct bonding) will be adapted as needed. The third part of the thesis will be dedicated to the electrical characterization and reliability tests of the obtained low temperature hybrid bonding.

Stocastic integrated power supplies based on emerging components

The widespread utilization of connected devices that process sensitive information necessitates the creation of new secure systems. The prevalent attack, referred to as power side-channel, involves the retrieval of encryption key information by analyzing the power consumption of the system. Integrating the system with its power supply management blocks can conceal the consumption of sensitive blocks, especially by utilizing various techniques to introduce randomized variations during power transfer. The CEA has wide experience in the design and testing of secure integrated circuits and it is exploring a new approach to DC-DC conversion that uses emerging devices available at CEA-Léti.
The work of the PhD researcher will be the following:
- Specification of integrated power supplies using switched-capacitor architecture.
- Study the circuit using emerging components and evaluate the improvement of its robustness against side channel attacks.
- Design of the integrated power supply in silicon technology.
- Performance and security characterization of the designed blocks and security primitives in
their whole.
The division of labor is 10% advanced study, 20% system architecture, 50% circuit design, 20% experimental measurement.

Design and construction of a snubber circuits associated with a power transistors in order to reduce disturbances during fast switching.

The thesis topic is aligned with the European Common Interest Project IPCEI ME/CT, which aims to enhance the value of the European semiconductor sector. It particularly investigates protection systems for direct current (DC) electrical networks against power overloads, short circuits, and electric arc incidents. These complex systems rely on power transistors to manage controlled disconnection of the electrical network, incorporating either separate functions or combined functions with a DC-DC converter.

Despite the abundant literature on the subject, it showcases a variety of approaches and configurations depending on the DC voltage and power levels involved. This project focuses on the activation of DC lines under severe conditions, initially at 400V (low-voltage DC, LVDC) and subsequently at 800V (medium-voltage DC, MVDC).

In the LVDC context, the emergence of GaN HEMT transistors (Gallium Nitride, with a breakdown voltage greater than 650V) has enabled the study of how well these components perform in line disconnection tasks. The rapid switching of the transistor necessitates precise control of the switching trajectory to ensure that the transistor operates within the safety limits specified by the manufacturer. Typically, this involves a snubber circuit for switching assistance. If an overvoltage cannot be avoided, a clamping device is added in parallel to the transistor. Experimental validation of such setups is quite challenging, especially when transistors are used in series or parallel, which motivates the development of alternatives that do not rely on a snubber circuit. However, due to the relative fragility of GaN transistors, this approach is not optimal.

Therefore, the project looks at integrating a switching assistance solution within the GaN transistor package. The production of the transistors and snubbers will utilize the facilities and techniques of the CEA-Leti cleanrooms, with microelectronic manufacturing processes optimized to allow their integration with silicon trench capacities, enabling co-integration with GaN transistors. The components will be assembled after being encapsulated.

Switching tests will initially be conducted within an inverter arm to assess various snubber circuit designs, switching frequencies, speeds, and temperatures. An ultra-fast metrological approach will be developed alongside the transistor design to enable measurements without compromising functionality.

In a later phase, the most promising solutions will also be validated within a back-to-back setup, in the particularly challenging case of opening an inductive DC line.

Study of innovative MOS gate stack for energy efficient SiC power transistors.

Silicon carbide (SiC) components represent the future of power electronics, surpassing silicon technologies in terms of temperature tolerance and power handling capability. At the heart of this evolution, CEA Leti plays a key role in the development of these new generation components, essential for applications such as electric vehicles, charging systems or photovoltaic installations. Our teams provide support to major manufacturers European countries by establishing pilot production lines for GaN and SiC components, as well as by developing SiC substrates with our industrial partners
This thesis aims to develop innovative technological approaches for the design of SiC MOS transistor gates and to evaluate their environmental impact to inform our technological choices. You will deepen the understanding of the physics of SiC MOSFETs by examining different gate architectures. and in
identifying the physical processes that restrict electron mobility in a SiC MOS channel. Questions such as the influence of stress on mobility and the possibility of separating carrier mobility from threshold voltage will be at the heart of your research.

Development and characterization of embedded memories based on ferroelectric transistors for neuromorphic applications

As part of CEA-LETI's Devices for Memory and Computation Laboratory (LDMC), you will be working on the development and optimization of FeFET transistors with amorphous oxide semiconductor channels for neuromorphic applications and near-memory computing.
The main challenge when co-integrating semiconductor and ferroelectric oxides is to perfectly assess and control a proper amount of oxygen vacancies, which govern both the ferroelectric properties of HfZrO2 and the conduction properties of semiconducting oxide, and impose major constraints on the manufacturing process steps.
The aim of the proposed internship is to conduct electrical measurements on various kind of elementary devices, stand-alone ferroelectric / semiconductive oxide films up to complete integreted FeFET devices. This will allow to propose an optimized process flow capable to provide both efficient ferroelectric switching performances (speed, low voltage capability…) together with state-of-the-art MOSFET performances (Ion/Ioff, subthreshold slope…).
The student will have access to a large amount of processed 200mm wafers, embedding a large variety of FeFET device flavors with different dimensions. Different process options will be available, either on already-available wafers or on request during the internship. For the latter, this will involve a close interaction with process experts (either deposition, annealing...) for modifying the FeFET process flow.
The student will benefit from state-of-the-art characterization platform, either for material characterization (XPS, UPS, XRD, TEM microscopy…) or for measuring the FeFET electrical performances.

Ultra-compact electronic actuation of micro-UAVs

Reducing the size of electronic systems for micro-drones is crucial for decreasing their weight, extending their battery life, and enhancing their maneuverability. This doctoral project aims to explore innovative solutions for energy management in integrated circuits designed for high-voltage actuation of micro-motors for very small drones (weighing about one gram and measuring a few mm³). The project encompasses micromechanics, the use of new small batteries developed by CEA-Leti, and the application of advanced microelectronic technologies. Through a collaboration between Gaël Pillonnet (CEA) and Patrick Mercier (University of California, San Diego - UCSD), you will benefit from a research environment at the forefront of technology, focused on the design of integrated circuits, and more specifically, on power management circuits (Power Management IC, PMIC). This work offers an exciting applicative dimension, with the integration of the circuit and batteries into an ultra-compact assembly intended for the activation of micro-motors. By joining our team, you will contribute to the advancement of cutting-edge technologies that will have a significant impact on the micro-drone sector.

Modeling and Optimization of 2D Material-Based Field-Effect Transistors: From Multi-Physics Simulations to Atomic-Scale Insights

Field-effect transistors employing 2D materials are emerging as promising candidates due to their superior mobility and atomic thinness. Nonetheless, this technology faces multiple challenges, including minimizing contact resistances, controlling variability, and optimizing short-channel transistors (< 10 nm). At CEA-Leti, a concerted experimental and computational effort is underway to address these issues and propel the development of 2D material-based technologies.

This doctoral research project is situated within this context, aiming to harness multi-physics simulations to evaluate and enhance the performance of 2D material-based FETs by exploring the interplay between technological parameters and device performance. The flexibility in choosing materials and geometric configurations opens the door to pioneering research directions. A pivotal aspect of this work will involve coupling Technology Computer-Aided Design (TCAD) simulations with ab initio methods to achieve a comprehensive understanding of the devices' structural and electronic behaviors at the atomic level.

The project benefits from access to state-of-the-art computational resources and software (Sentaurus, VASP, GPAW, etc.), supported by CEA-Leti's expertise in simulation methodologies and close collaboration with experimental teams. This doctoral endeavor offers a unique opportunity to develop a wide-ranging skill set in electronic device simulation, contributing to the scientific community through presentations at leading international conferences and publications in esteemed journals.

Molecular dynamics simulation of phase change in Ge-rich GeSbTe materials

The goal of this thesis is to study the phase change of Ge-rich GST with molecular dynamics (MD) simulations using equivariant graph neural networks interatomic potentials (GNN-IP). The candidate will train a GNN-IP model on ab initio reference calculations of Ge-rich GST in order to describe amorphous and crystalline phases. The GNN-IP will be used to compute thermodynamic and kinetic properties of the phase transitions. In a second step, further developments including the effect of impurities and the impact of an electrical field on the phase change will be addressed. Finally, physical parameters computed from MD simulations will be employed to improve our in-house mesoscopic model based on the phase-field method.