Energy-minimizing associative neural networks using resistive memories
This PhD project aims to develop Hopfield-type associative neural networks that perform inference through energy-minimizing dynamics.
The goal is to exploit these dynamics for image denoising and reconstruction close to the sensor, under strict energy and latency constraints.
The network synapses will be implemented in ReRAM crossbar arrays, enabling analog in-memory matrix-vector operations.
The work will focus on architecture dimensioning while accounting for array size, weight quantization, device variability and endurance limits.
Reference models will be developed in PyTorch to evaluate alternative neural dynamics and hardware mapping strategies.
Patch-wise image denoising will serve as the main use case to quantify trade-offs between reconstruction quality, latency and energy consumption.
Particular attention will be paid to the robustness of the networks against hardware non-idealities such as noise, variability and memory drift.
The project will also investigate local on-chip learning mechanisms, allowing slow adaptation to changes in the sensor, scene or memory devices.
These learning rules must remain compatible with the endurance constraints of resistive memories.
Ultimately, the PhD should provide hardware-sizing guidelines and support the design of an experimental test vehicle.
The broader scientific objective is to demonstrate that dynamic associative inference can become an efficient, robust and low-power building block for edge AI.
New methodologies for analyzing the impact of crystal defects on the electrical performance of SiC power devices
In our past studies on SiC power devices, the analysis of electrical performances on diodes [1] (idem for future MOSFETs) must take into account the impact of material's defects at the epitaxy and substrate level.
Initially, the thesis work will consist of setting up tools dedicated to our needs in the SiC team. The specifications for these tools have already been established as part of the internship currently underway within the LAPS laboratory. These AI tools will be able to be trained on already existing datasets (SiC diode batches: with electrical data, defect mappings) and complete the previous manually carried out analyses.
In a second phase, the use of the developed tools will be applied to new manufactured and characterized batches. The range of data will then be completed by considering new component architectures (diodes and power MOSFETs), new material characterizations (defects characterization from other tools being installed at Leti, or even with external collaborators: see Line Pilot WBG, see Soitec), new entries (images of defectivity, obtained during the components fabrication in the clean rooms).
Note that the approach applies i) in the case of power to other materials (GaN, diamond, Ga2O3...), ii) also potentially to any component on semiconductor (memory, transistor, photonic, quantum...).
Junction defect characterization of low therMal Budget SOI MoSFET
Join CEA-Leti and CROMA to analyze in depth junctions of a new technology. Indeed, our transistors are fabricated under restricted thermal budget for 3D sequential integration, making dopants activation very challenging! Our team will support you technically and scientifically to conduct this work. Some data are already available and waiting for your analysis.
During this PhD, you will have the opportunity to perform all theses steps:
From the idea (simulation, bibliography, TCAD) 20%
Processes understanding (implantation, SPER) 10%
Integration & cleanroom fabrication management 10%
Characterization (physical & electrical: noise, DLTS…) 50%
Valorization (presentations, article) 10%
This PhD offers a unique chance to be at the forefront of technological innovation and to make a significant impact in the field of advanced SOI. Join us and take the first step towards an exciting career in research and development!
With a background in microelectronics or nanotechnologies, you are curious about integration of new processes, not afraid about equations and liked semiconductors classes at school. You want to solve complex puzzles and enjoy collaborating with others to figure out innovative solutions.
Topologically Isolated Mode Acoustic Resonators
Timing is a key function in electronic circuits. Beyond on-chip signals synchronization, it also allows the synchronization of wireless data transmissions. Accurate time references require stable frequency sources, which also benefit to sensor applications. The gold standard for time or frequency generation is still quartz resonators, which are however bulky and difficult to miniaturize. Research is therefore still ongoing to provide high quality factor (> 10,000) resonators, ideally capable of operating at frequencies of several GHz. A key to reach such high quality factors is to confine strongly the mechanical vibration of micro-size structures in order to make them insensitive to external perturbations. Recently, the field of topological acoustics has demonstrated the capability to confine elastic waves in very small volumes concentrated at the interface between periodic structure, and to provide extremely high quality factor resonances.
This PhD position focuses on exploiting topologically protected modes in piezoelectric microstructures to provide next generations of high quality factor resonators, which may be used in oscillators or even filter circuits. Leveraging the know-how of CEA Leti in the design and fabrication of such components, the PhD will be part of an international collaboration with well established academic laboratories (Politecnico di Milano, Imperial College FEMTO-ST Institute) and industrial partners.
The candidate will model and design structures supporting topologically protected modes, combinining finite element simulations with simplified numerical approaches which reduce computation times. He will follow the fabrication of demonstrators in collaboration with the process integration teams in the CEA Leti clean rooms, and carry on measurements of the proposed resonators.
High-Endurance Chalcogenide Memories for Next-Generation AI
Discover a unique phd opportunity where you will dive into the heart of innovation in memory technologies. You will develop strong expertise in areas such as electrical characterization and the understanding of degradation phenomena in chalcogenide-based memories.
By joining our multidisciplinary teams, you will play a key role in studying and improving the endurance of Phase-Change Memory (PCM) and Threshold Change Memory (TCM) devices—two promising technologies for high-performance artificial intelligence applications. You will take part in innovative projects combining scientific rigor and applied research on nanoscale devices, working closely with another CEA PhD student who conducts advanced physico-chemical analyses (TEM) to investigate degradation mechanisms.
You will have the opportunity to contribute actively to tasks such as:
Electrical characterization of PCM and TCM devices to analyze cycling-induced degradation
Development and evaluation of innovative programming protocols to extend endurance limits
Proposing solutions to improve the reliability and performance of next-generation memories
Regular collaboration and discussion with the CEA PhD student to interpret TEM results and draw conclusions about degradation mechanisms
Advancing All-Solid-State Microbatteries: Interface Stabilization and Degradation Mitigation for Long-Term Reliability
This PhD project focuses on advancing all-solid-state microbatteries for miniaturized energy storage applications, such as wearable electronics, IoT systems, and implantable medical technologies. The research aims to stabilize and mitigate degradation at the electrode/electrolyte interfaces, which are critical bottlenecks in solid-state microbattery performance. The project involves two main research axes: (1) the study and optimization of ultrathin films (sub-nanometer to nanometer scale deposited by ALD) for engineering the interfaces in LiCoO2/LiPON/Li stacks, and (2) a fundamental investigation of the mechanisms responsible for interface degradation. The study will involve the fabrication and characterization of partial and complete stacks using techniques like cyclic voltammetry (CV), electrochemical impedance spectroscopy (EIS), X-ray diffraction (XRD), and scanning electron microscopy (SEM). The incorporation of alloying metals (e.g., Ag, Au) between the buffer layer and lithium will also be explored to enhance lithium-metal interface stability. The expected outcomes include an optimized microbattery stack capable of exceeding 1,000 cycles with minimal increase in interfacial resistance and a comprehensive framework describing degradation mechanisms and buffer layer effects.
Study of mechanical stress on Solid State Micro-batteries
CEA-Leti provides integrated microstorage solutions, including solid state (or solid electrolyte) microbatteries. Solid-state micro-batteries are among the most promising microstorage technologies for applications in several fields such as the internet of things and implantable devices for medical use. The objective of this thesis is to study the impact of mechanical stresses on microbatteries, particularly during microbattery charge/discharge cycles. To this end, two approaches will be considered: experimental study with the development of mechanical test benches and numerical simulation.
The PhD student's work will begin with the development of test benches, the first of which will apply variable pressure to the surface of a microbattery during charge/discharge cycles. He/she will be required to develop the pressure measurement equipment. Once the mechanical test bench is operational, other characterizations, such as measuring anode deformations, will be considered. In parallel with this experimental work, a mechanical model will be developed. This model will be progressively refined using the experimental results obtained with the mechanical test bench, and new characterizations may be implemented in order to obtain the mechanical properties of the different materials used. Ultimately, the objective will be to propose the integration of new layers to improve the mechanical performance of microbatteries during cycling.
Study of Failure Modes and Mechanisms in RF Switches Based on Phase-Change Materials
Switches based on phase change materials (PCM) demonstrate excellent RF performance (FOM <10fs) and can be co-integrated into the BEOL of CMOS processes. However, their reliability is still very little studied today. Failure modes such as heater breakage, segregation, or the appearance of cavities in the material are shown during endurance tests, but the mechanisms of these failures are not discussed. The objective of this thesis will therefore be to study the failure modes and mechanisms for different operating conditions (endurance, hold, power). The analysis will be carried out through electrical and physical characterizations and accelerated aging methods will be implemented.
Reinventing Microspeakers: From Planar Limits to 3D Designs for Ultrasonic Modulation Loudspeakers
Are you looking for a PhD at the intersection of acoustics, microsystems, and innovation? This project may be for you.This PhD focuses on the design, fabrication, and experimental validation of an innovative MEMS microspeaker concept based on ultrasound demodulation. Conventional micro transducers face a major limitation: they require large planar surfaces to displace sufficient air at low frequencies, leading to increased device size and manufacturing cost. This project explores an alternative architecture using vertical blade structures, exploiting the third dimension together with ultrasound demodulation to improve electro acoustic efficiency while reducing device footprint.
Building on preliminary exploratory work, the objective of the PhD is to develop a complete MEMS loudspeaker demonstrator. The work will include physical modeling, multi-physics simulation, device design optimization, microfabrication process development, and experimental electro acoustic characterization. Particular attention will be given to identifying and overcoming the physical and technological limitations governing device performance.
The candidate will design and simulate the device architecture and contribute to the definition of the fabrication process in close interaction with microfabrication specialists. The PhD work will also include acoustic and electrical characterization of the fabricated devices in order to validate the proposed concepts and compare experimental results with modeling predictions. The PhD will take place in a multidisciplinary environment, providing access to expertise in acoustics, MEMS design, microfabrication processes, and electro acoustic measurement.
3D interconnects for the design and fabrication of quantum processor units
To increase the performance of quantum computers, three-dimensional (3D) integration is now the key! Using technologies such as flip-chip bonding, multi-layer wiring or even through-silicon vias (TSV), 3D integration offers solutions to increase the number of qubits on a processor, reduce signal loss and cross-talk and even improve thermal management. All of these aspects are essential to continue scaling qubits to achieve fault-tolerant quantum computing.
Our team is developing 3D interconnect technologies (e.g. superconducting microbumps and TSV) for the next generation of quantum processors. This thesis will focus on the electrical and radiofrequency characterization of such interconnects and of the quantum devices integrated nearby to gain knowledge on how these 3D technological bricks may impact the quantum properties.
This position will bring you at the boundary between material, technological and physical challenges of quantum systems. You will work with teams from CEA-LETI and CEA-IRIG. As a PhD candidate, you will take part in the design and layout of test vehicles and in their fabrication. You will also lead the low temperature measurements of the fabricated samples, perform the associated analysis and write reports.