The impact of intrinsic and of extrinsic defects on the dynamic Ron and off-state leakage current of lateral GaN power devices

The intentional doping of lateral GaN power high electron mobility transistors (HEMTs) with carbon (C) impurities is a common technique to reduce buffer conductivity and increase breakdown voltage. However, this comes at the cost of increased intrinsic defects together with degraded dynamic on-resistance (Ron) and current-collapse effects.
The aim of this project is compare the performance of HEMTs devices containing different quantities of extrinsic defects (such as C atoms) and intrinsic defects (such as dislocations), as a function of growths conditions to guide toward optimized buffer structure with good dynamic Ron and low vertical leakage simultaneously.

Investigate electron and hole transport layers for high temperature stability III-V quantum dot photodiode devices

Colloidal Quantum Dots (QD) are novel building blocks for the fabrication of image sensors with high performance tunable light detection in the SWIR wavelength range but currently exhibit undesired degradation under high thermal stress. Thermal degradation can be significantly improved by optimizing the device materials (contacts, hole transport layer (HTL), electron transport layer (ETL) and encapsulation), film thicknesses, and deposition processes used to make quantum film (QF) photodiode devices. As such, a detailed investigation into many different HTL, ETL and top electrode materials will be pursued to find the best candidates to overcome the current limitations. Materials selection and deposition processes for these layers will be chosen and studied among a variety of existing materials developed at LETI. QD films with tunable absorption from 1-2.5 µm will be prepared by STMicroelectronics and CEA-IRIG in collaboration with other partners. The QD patterning step for the fabrication of the devices and the electro-optical testing will be performed internally at LETI with support from STMicroelectronics.

Line edge roughness extraction with a sub-nanometer resolution

Within the European Chips Act, CEA-Leti is strongly committed to support the reduction of component dimensions to reach the future technological nodes (below 10 nm). To detect and account the line edge roughness becomes critical for such small dimensions since ‘the few Angstrom error’ becomes critical (several % of error) for sub-10nm devices.
This PhD work will focus mainly on the use of CD-SAXS to define the sensibility of the technique. To do so, we propose to follow two main complementary directions: first to perform simulations with tools under developments to identify the exact impact of roughness on a CD-SAXS pattern; and secondly to lead the experimental measurements on samples specifically designed at the CEA-LETI with controlled roughness. . CD-SAXS measurements will be done both on the laboratory equipment at the CEA as well as at synchrotrons (ESRF, NSLS-II). These results will be compared with results obtained from CEA-LETI cleanroom metrology equipment, such as AFM-3D and CD-SEM.
This PhD will take place between the Nanocharacterization platform of the CEA–LETI witch offer world-class analytical techniques and state-of-the-art instruments and the cleanroom metrology team from the CEA-LETI.

Lithography process and design rules co-optimisation for advance microelectronics

Historically, the development of integrated circuit performance has been based on the reduction in size of individual components. The main driving force behind this miniaturization is photolithography, a key step in the semiconductor component manufacturing process. This process consists in reproducing the design of the circuits to be produced in a photosensitive resin. These complex patterns are generated in a single exposure. Light from an ultra-low-wavelength light source (DeepUV) projects a mask image onto the resin. The higher the optical resolution, the greater the miniaturization of the circuits.

When developing new technologies in microelectronics (e.g. FDSOI 10nm, advanced photonics), it is necessary to establish circuit design rules and in parallel to develop photolithography processes to reproduce these designs on the chip. The aim of this thesis is to build bridges between these 2 distinct but closely interwoven worlds, in order to co-optimize their development.

Starting from a practical case for advanced technologies, the thesis work will address the following areas/problems:
- Improving the accuracy and cycle time of the digital lithography models calibration needed to correct optical proximity effects (OPC);
- Using CD-SEM characterizations, identifying borderline design configurations and adjusting design rule constraints accordingly;
- Designing innovative patterns that optimize the dimensional space covered, and evaluating them with a rigorous lithography simulation tool and/or experimentally;
- Integrating lithography results into design tools to establish causal links with device electrical performance.

The thesis will be carried out in Grenoble, at CEA-Leti, internationally recognized for the excellence of its research in the field of microelectronics, and will benefit from the exceptional facilities of the institute's clean room. In particular, the student will be attached to the Laboratoire de PAtterning Computationnel (LPAC), which is exploring ways of improving lithography and etching processes by relying heavily on digital tools, in close partnership with a number of major industrial players. The lab brings together around fifteen people from a wide range of complementary backgrounds (Masters students, student engineers, PhD students, technicians, engineers and researchers, on fixed-term or permanent contracts), who are used to working closely together to give everyone the chance to fulfil their potential and contribute collectively to the progress of the laboratory's work.
The student will be expected to publish and share his/her work at various international conferences.

Quantification of strategic binary compounds by hard X-ray photoemission (HAXPES) and combined surface analysis

The main objective of the thesis is to provide reliable support to the processing of front-end materials for advanced FD-SOI technologies. To achieve this, methodologies for elemental quantification focused on the use of hard X-ray photoelectron spectroscopy (HAXPES) will be developed and validated through a collaborative framework at multiple levels, both internal and industrial.
These collaborations will enable to pool upstream work aimed at a better understanding of quantification in HAXPES at all levels (intensity measurement, types of sensitivity factors used, measurement reproducibility).
In a second step, the protocols will be applied to the targeted technological materials and then optimized. The targeted materials are primarily silicon and germanium compounds contributing to the optimization of the channels of advanced FD-SOI transistors, such as Si:P, SiGe, and their derivatives (GeSn, SiGe:B). A combined analytical approach involving other nanoscale characterization techniques will be strengthened by identifying the most appropriate techniques to produce reference data (ToF-SIMS, RBS, etc.).
In a third step, multi-scale aspects will be developed. In particular, they will aim to investigate to what extent the composition measured by HAXPES on a material developed upstream of transistor integration steps (for process deposition optimization) compares to that determined by other techniques (atom probe tomography, TEM-EDX, TEM-EELS) at the end of nanometric device integration.

Could convolutional neural network bring benefits in nanometrics etch processing?

The development and production of energy-efficient electronic components is a major challenge for the microelectronics sector. To answer such a challenge, CEA-Leti and CNRS-LTM does not only focus on building, making and testing new architecture. We also focus on developing greener process and investigating novative solutions to reduce the environmental impact.
Precedent works on process step simulation, based on numerical approach, have already been done in CNRS-LTM institute using HPEM tools specialized on plasma etching or at CEA-LETI considering electronic microscope image processing. To be fully operational, these works still need experimental proof. Process characterization could also be another blocking point, whereas the lateral top view dimension could easily be acquire, for example using CDSEM (10 images/mn), the depth and geometry etch profile need complex and time consuming characterization such as TEM (1 image/d). By combining numerical simulation results, physical characterization and fast CDSEM image acquisition technics the PhD student would be able to train a convolutional neural network in order to predict etch profile geometry. These predictions will be helpfully in the future process development and will bring benefits in terms of time to success and financial/environmental cost reduction.

Realization of MOSFET gates at the sub-10nm node on FD-SOI

As part of the NextGen project and the European ChipACT to ensure the sovereignty and competitiveness of France and Europe in terms of electronic nano-components, CEA-LETI is launching the design of new FD-SOI chips. Already present daily in the automotive or connected object areas, 28-18nm FD-SOI transistors are produced in large volumes by microelectronics founders such as STMicroelectronics. This technology is based on an innovative architecture allowing the production of transistors that are faster, more reliable, and less energy-consuming than transistors on massive substrates. The move to the 10nm node will improve the performance of this technology while being compatible with the issues of energy efficiency and the challenges of miniaturization.
The Field-Effect Transistor (FET) at the 10nm node requires a complex silicon/high-k insulator/metal gate stack. The addition of the high-k dielectric enables to reduce the leakage currents of the gate, but its use coupled with the miniaturization of the components induces new difficulties in the electrical behavior of the FET related to the heterogeneity of the materials constituting the gate stack. To try to resolve these difficulties, this doctorate focuses on an assembly including the deposition of extremely thin metal films on high-k and allowing adjustment of the threshold voltage of the transistors. To study these layers and carry out metallic deposits, CEA-LETI is equipped with PVD equipment for multi-cathode co-sputtering on 300mm silicon wafers. It will make it possible to produce complex alloys and metallic layers adjusted in composition with thickness control at the atomic scale.

Impact and cohabitation of Lithium on a microelectronics platform

Context: Lithium-based materials, whether thin layers or bulk material, are of great interest for varied applications (batteries, RF components…). However, their cohabitation with other “standard” materials for microelectronics requires special attention regarding dissemination in the clean room and a potential impact on electrical performances of devices. Indeed, as a precaution, these materials are “confined” on dedicated manufacturing lines, without full knowledge of their potential effect on the manufactured devices. This work aims at understanding the phenomena leading to lithium dissemination, to propose solutions to keep it under control and to take advantage of possible beneficial effects.
Mission: During this Ph.D. thesis, you will work in close collaboration with a multidisciplinary team in CEA and with their partners. This will involve highlighting the possible vectors of Lithium dissemination in common manufacturing spaces in clean rooms. Furthermore, you will define a methodology to identify and quantify Lithium in various materials and at their interfaces using physicochemical characterization tools available to the “Ion Beams” and “Operational Metal Contamination” (clean room) teams from the Surfaces & Interfaces Analysis Laboratory (LASI). A large part of the work will rely on ion beam analysis technics such as secondary ion mass spectrometry. This implementation will allow studying the mechanisms and kinetics of lithium diffusion as well as to evaluate its impact on the performance of “microelectronics” devices.
Profil: Chemist, physicist, engineer, etc., you have knowledge in chemistry/physics on materials/ semiconductors. Holder of a Bac+5, you are curious, rigorous, creative and wish to participate in a 3-year research project in support of microelectronics.

Intrafield placement error optimisation for advanced integration nodes

As part of the microelectronics growth plan, driven by the European directive France 2030, CEA Leti is acquiring new state-of-the-art tools and developing new technologies for future applications.
The challenge is to develop several technological building blocks enabling the industrial transfer of microelectronic processes down to the 10nm technology node.
Lithography is the most critical step in the manufacturing of a component, as it enables the definition of addressed patterns (dimensions, shapes, etc.), which is why R&D work on this step requires particular attention to meet the needs of the industry.

Up to now, it was enough to monitor the two key parameters in order to ensure the device performances:
- Critical dimension uniformity (CDU) across the wafer
- Overlay (OVL), which represents the relative intra-field position of two lithography levels compared to their theoretical position.
However, reducing pattern size requires a more global view of these control parameters. In this case, the term “placement error” is well more adapted. It combines CDU and OVL, answering the question: where "trully" is the pattern in relation to its ideal position?

Many studies (i.e. Mulkens J., et al. Proc. SPIE 1014505, 2017) have shown a significant dependency relation of placement error with several parameters, such as follow :
Optical proximity correction (OPC), registration error (mask related), resists, exposition & development step, overlay, CDU or resist roughness.
The placement error budget is therefore becoming very critical in the industry, and is highly correlated with the state-of-the-art capabilities of the equipment to ensure the processes.

The aim of this thesis will therefore be to understand the technological issues raised by process integration on placement errors at field and wafer scale. In addition, solutions will be proposed for characterizing intra-field deformation and optimizing intra-field performance in 193 immersion lithography to meet the requirements of sub-10nm technologies.

The main axis of this thesis could be described as follow:
1/ To Acquire an understanding of the topic challenges by deep literature monitoring and knowledge of the strategies in place currently in microelectronics.
2/To Get acquianted with cleanroon environnment and to learn working on new generation equipments, specifically on 193i lithography scanner and metrology tools recently installed. Several formations will be displayed.
3/ All over the thesis, to publish (scientific reviews) and share results and achievements on different conferences
4/ Thesis manuscrip writting & presentation

This work is integrated into the Lithography laboratory (LLIT) of CEA Leti Silicon plateform division (DPFT). You will be part of a dynamic and multidisciplinary team: from optical photolithography process to alternative lithography such as nanoimprint and ebeam lithography expertise, on state-of-the art clean room equipments. The team works in synergy with industrial partners that allows an efficient transfer of Leti innovations.

3D chemical investigation of 10 nm FDSOI CMOS devices.

The development of 10 nm FDSOI (Fully Depleted Silicon On Insulator) technology leads to new constraints on the architecture of transistors. The gate width (10 nm) requires a specific integration of the gate that controls the threshold voltage. The variability of the threshold voltage depends on the concentration, spatial distribution and chemical nature of dopants in the source and drain area. Therefore, it is crucial to understand the impact of growth conditions of the metallic gate, source, drain and annealing temperature to activate the dopant. To master these new constraints, the use of characterization techniques that can identify the structural and chemical mechanisms (distribution and quantification) acting in the gate, source and drain will be essential. Among all the chemical characterization techniques, Atom Probe Tomography is the technique of choice that offers a 3D chemical and quantitative mapping of a sample with nanometre scale resolution.
The objectives of this PHD will be to: (i) develop 3D characterization methodologies (distribution and chemical composition of species within the gate and source-drain area) of transistors, (ii): investigate the impact of growth conditions, annealing temperature activating the dopants and implantation dose. The PHD student will try to model the formation mechanisms of the observed chemical compounds.