Atomic layer deposition of vanadium sulfide contacts for next-generation transistors based on 2D dichalcogenides

The main purpose of this research is to develop and evaluate the potential of atomic layer-deposited vanadium sulfide as an efficient contact on next-generation transistors based on 2D dichalcogenide semiconductors. The student will achieve atomic layer deposition (ALD) of VSx films in a dedicated reactor at LMGP allowing in situ optical and chemical characterization along with structural and chemical characterization with synchrotron radiation, in order to get an insight into the growth mechanisms and structural changes occurring during the crystallization. She/he will investigate the electrical properties of the VSx films and VSx/MoS2 heterostructures.

Seeking the maximal active dopant concentration in Si using nanosecond laser annealing

In conventional CMOS technology, source & drain regions of transistors are formed by ion implantation of selected impurities (B, P) in silicon or SiGe alloy, and a subsequent thermal treatment to cure the crystal and electrically activate the dopants. In the case of 3D-sequential integration, an architecture in which at least tow levels of transistors are superimposed, the thermal budget for the fabrication of the upper level transistors is limited, to avoid any degradation of the bottom level. Classical annealings during a few seconds/ minutes at 600-1050°C are not anymore possible. One can choose to switch to Nanosecond Laser Annealing (NLA), enabling very short anneals with heat confined in the first tens of nanometers thanks to its UV laser and very short pulse duration. Depending on the amount of heat provided to the Si or SiGe layer by NLA, various phenomena can be encountered. When heat amount is sufficient, the layer can melt and solidify. On the other side, when heat amount does not exceed the melt threshold, solid phase epitaxial regrowth (SPER) can take place. In both cases, the extreme cooling rate gives access to high active dopant concentration, eventually beyond the solubility limit. However, maximal achievable active dose (phosphorus and boron in silicon, boron in SiGe) are not known, for both solid and liquid regimes.

Scheduling adapted to R&D cleanrooms

In the midst of digital transition, characterized by the rapid development of new technologies, this subject aims to participate in the automation of decision support processes in a dynamic and complex environment, and to reduce cycle times in an R&D environment, increasingly subject to an injunction of efficiency.
In the current context marked by great uncertainty and multiple crises (geopolitical, economic and ecological), the microelectronics manufacturing industry is facing global competition. To face these challenges, this thesis project aims to develop resolution methods for a scheduling problem on complex machines within flexible workshops, taking into account the dynamic nature and complexity of the microelectronics production environment.
The objective is to propose approaches offering robust and industrially relevant solutions to meet these challenges. Robustness will be assessed using appropriate risk indicators, while industrial relevance will be measured via previously identified performance indicators. The proposed resolution approaches will be evaluated through numerical experiments carried out on benchmark instances and industrial cases, and more particularly on the WIP of LETI cleanrooms. In particular, taking into account equipment campaigns and long downs will be one of the work areas of the thesis. The specificities of the different workshops (high work in progress and short processing time, limited work in progress with long processing time) will also be studied in order to provide a global tool, adapted to R&D clean rooms, and efficient.

The impact of intrinsic and of extrinsic defects on the dynamic Ron and off-state leakage current of lateral GaN power devices

The intentional doping of lateral GaN power high electron mobility transistors (HEMTs) with carbon (C) impurities is a common technique to reduce buffer conductivity and increase breakdown voltage. However, this comes at the cost of increased intrinsic defects together with degraded dynamic on-resistance (Ron) and current-collapse effects.
The aim of this project is compare the performance of HEMTs devices containing different quantities of extrinsic defects (such as C atoms) and intrinsic defects (such as dislocations), as a function of growths conditions to guide toward optimized buffer structure with good dynamic Ron and low vertical leakage simultaneously.

Investigate electron and hole transport layers for high temperature stability III-V quantum dot photodiode devices

Colloidal Quantum Dots (QD) are novel building blocks for the fabrication of image sensors with high performance tunable light detection in the SWIR wavelength range but currently exhibit undesired degradation under high thermal stress. Thermal degradation can be significantly improved by optimizing the device materials (contacts, hole transport layer (HTL), electron transport layer (ETL) and encapsulation), film thicknesses, and deposition processes used to make quantum film (QF) photodiode devices. As such, a detailed investigation into many different HTL, ETL and top electrode materials will be pursued to find the best candidates to overcome the current limitations. Materials selection and deposition processes for these layers will be chosen and studied among a variety of existing materials developed at LETI. QD films with tunable absorption from 1-2.5 µm will be prepared by STMicroelectronics and CEA-IRIG in collaboration with other partners. The QD patterning step for the fabrication of the devices and the electro-optical testing will be performed internally at LETI with support from STMicroelectronics.

Titanium silicide integration on future generation of low power transistor

In the ultra-competitive world of semi-conductor industry, CEA work on development of very low power transistor with high performances called FD-SOI for European industry. The PhD will take place inside CEA-LETI, worldwide known for its expertise on FD-SOI field. Inside LETI, you will be part of a 6 to 7 people team working on silicides.

Your goal: develop tomorrow silicide and understand the best way to integration inside transistor fabrication scheme. Silicide, an alloy between a metal and the silicon, is a key element inside an electronic circuit because it is the link between passive part (connexion wires) and active part (transistor). In order to reduce consumption, it is essential to reduce the resistance to current flow of these alloys. To do this, you will need to study crystalline phases, resistivity and thermal stability of the silicides thanks to characterisation techniques such as X-ray diffraction, electronic microscopy or electrical measurement in collaboration with field expert. Experiment of X-ray diffraction on synchrotron such as ESRF at Grenoble could also be consider. You will also need to develop new integration scheme of those silicides in a complex fabrication flow (thermal treatment, ionic implantation, metal deposition …). Finally, you will have the opportunity to characterize electrically the influence of the silicide integration scheme on the transistor performances.

Realization of MOSFET gates at the sub-10nm node on FD-SOI

As part of the NextGen project and the European ChipACT to ensure the sovereignty and competitiveness of France and Europe in terms of electronic nano-components, CEA-LETI is launching the design of new FD-SOI chips. Already present daily in the automotive or connected object areas, 28-18nm FD-SOI transistors are produced in large volumes by microelectronics founders such as STMicroelectronics. This technology is based on an innovative architecture allowing the production of transistors that are faster, more reliable, and less energy-consuming than transistors on massive substrates. The move to the 10nm node will improve the performance of this technology while being compatible with the issues of energy efficiency and the challenges of miniaturization.
The Field-Effect Transistor (FET) at the 10nm node requires a complex silicon/high-k insulator/metal gate stack. The addition of the high-k dielectric enables to reduce the leakage currents of the gate, but its use coupled with the miniaturization of the components induces new difficulties in the electrical behavior of the FET related to the heterogeneity of the materials constituting the gate stack. To try to resolve these difficulties, this doctorate focuses on an assembly including the deposition of extremely thin metal films on high-k and allowing adjustment of the threshold voltage of the transistors. To study these layers and carry out metallic deposits, CEA-LETI is equipped with PVD equipment for multi-cathode co-sputtering on 300mm silicon wafers. It will make it possible to produce complex alloys and metallic layers adjusted in composition with thickness control at the atomic scale.

Impact and cohabitation of Lithium on a microelectronics platform

Context: Lithium-based materials, whether thin layers or bulk material, are of great interest for varied applications (batteries, RF components…). However, their cohabitation with other “standard” materials for microelectronics requires special attention regarding dissemination in the clean room and a potential impact on electrical performances of devices. Indeed, as a precaution, these materials are “confined” on dedicated manufacturing lines, without full knowledge of their potential effect on the manufactured devices. This work aims at understanding the phenomena leading to lithium dissemination, to propose solutions to keep it under control and to take advantage of possible beneficial effects.
Mission: During this Ph.D. thesis, you will work in close collaboration with a multidisciplinary team in CEA and with their partners. This will involve highlighting the possible vectors of Lithium dissemination in common manufacturing spaces in clean rooms. Furthermore, you will define a methodology to identify and quantify Lithium in various materials and at their interfaces using physicochemical characterization tools available to the “Ion Beams” and “Operational Metal Contamination” (clean room) teams from the Surfaces & Interfaces Analysis Laboratory (LASI). A large part of the work will rely on ion beam analysis technics such as secondary ion mass spectrometry. This implementation will allow studying the mechanisms and kinetics of lithium diffusion as well as to evaluate its impact on the performance of “microelectronics” devices.
Profil: Chemist, physicist, engineer, etc., you have knowledge in chemistry/physics on materials/ semiconductors. Holder of a Bac+5, you are curious, rigorous, creative and wish to participate in a 3-year research project in support of microelectronics.

3D chemical investigation of 10 nm FDSOI CMOS devices.

The development of 10 nm FDSOI (Fully Depleted Silicon On Insulator) technology leads to new constraints on the architecture of transistors. The gate width (10 nm) requires a specific integration of the gate that controls the threshold voltage. The variability of the threshold voltage depends on the concentration, spatial distribution and chemical nature of dopants in the source and drain area. Therefore, it is crucial to understand the impact of growth conditions of the metallic gate, source, drain and annealing temperature to activate the dopant. To master these new constraints, the use of characterization techniques that can identify the structural and chemical mechanisms (distribution and quantification) acting in the gate, source and drain will be essential. Among all the chemical characterization techniques, Atom Probe Tomography is the technique of choice that offers a 3D chemical and quantitative mapping of a sample with nanometre scale resolution.
The objectives of this PHD will be to: (i) develop 3D characterization methodologies (distribution and chemical composition of species within the gate and source-drain area) of transistors, (ii): investigate the impact of growth conditions, annealing temperature activating the dopants and implantation dose. The PHD student will try to model the formation mechanisms of the observed chemical compounds.

Enabling patterning fidelity analysis over millimetric distances for curvilinear mask data-preparation : application to photonics devices.

Integrated silicon photonics, which consists of using manufacturing processes from the microelectronics industry to produce photonic components, is considered a critical future technology for very high-speed communications and computing applications.
The creation of silicon photonics devices requires the manipulation of fully curved designs (so-called non-Manhattan). This gives rise to numerous challenges during their manufacturing, and particularly during the design stage of advanced photolithography masks. In order to determine the optimal masks, optical effects compensation (OPC) algorithms are systematically applied. The latter are particularly difficult to implement in the particular case of curvilinear patterns.
The accuracy with which OPC models are able to anticipate pattern printing performance can be assessed using CD-SEM on specific, simple, small structures in a single orientation. However, Photonic devices (for example, waveguides) are continuous, up to a few millimeters long, and cover all orientations in space. A broad and precise metrology of such objects does not exist, making it impossible for OPC engineers to diagnose the quality of the devices produced on the product.
The objective of the thesis is to develop a method for precise, large-scale dimensional measurement of Photonic structures. In particular, we will seek to implement solutions for stitching SEM images and extracting contours, with the development of dedicated metrics. The thesis proposes in particular:
- the study of metrological and scripted solutions to enable characterization by CD-SEM on a large scale, typically by combining several images.

- the implementation of extraction of contours of curved patterns on recombined images.

- the development and implementation of innovative 2D metrics to allow the measurement of curved objects, then their comparison with each other (or with a reference).

- the inclusion of real large-scale contours in optical simulation software (Lumerical, FDTD) to characterize the real performance of the devices.

The thesis will take place for 3 years between the STMicroelectronics site (Crolles) and that of CEA-LETI (Grenoble), in a context of strong collaboration between the teams of the two organizations.

The doctoral student will have access to clean rooms and state-of-the-art industrial and/or research equipment, as well as commercial reference software. You will benefit from all the technical expertise of the supervisory teams at STMicroelectronics and CEA-LETI in photolithography, metrology, image processing and applied IT development (Python).