The technology choice in the eco-design of AI architectures

Electronic systems have a significant environmental impact in terms of resource consumption, greenhouse gas emissions and electronic waste, all of which are experiencing a massive upward trend. A large part of the impact is due to production, and more particularly the manufacturing of integrated circuits, which is becoming more and more complex, energy-intensive and resource-intensive with new technological nodes. The technology used for the implementation of a circuit has direct effects on the environmental costs for production and use, the lifespan of the circuit and the possibilities of several life cycles in a circular economy perspective. The technological choice therefore becomes an essential step in the ecodesign phase of a circuit.
The thesis aims to integrate the exploration of different technologies into an eco-design flow of integreted circuit. The purpose of the work is to define a methodology for a systematic integration of the technological choice into the flow, with identification of the best configuration of the architecture implemented for maximizing the lifespan and taking into account the strategies of circular economy. The architectures targeted by the thesis fall into the field of embedded AI, which is experiencing an upward deployment trend and involves major societal challenges. The thesis will constitute a first step in research towards sustainable embedded AI.

AI-assisted generation of Instruction Set Simulators

The simulation tools for digital architectures rely on various types of models with different levels of abstraction to meet the requirements of hardware/software co-design and co-validation. Among these models, higher-level ones enable rapid functional validation of software on target architectures.

Developing these functional models often involves a manual process, which is both tedious and error-prone. When low-level RTL (Register Transfer Level) descriptions are available, they serve as a foundation for deriving higher-level models, such as functional ones. Preliminary work at CEA has resulted in an initial prototype based on MLIR (Multi-Level Intermediate Representation), demonstrating promising results in generating instruction execution functions from RTL descriptions.

The goal of this thesis is to further explore these initial efforts and subsequently automate the extraction of architectural states, leveraging the latest advancements in machine learning for EDA. The expected result is a comprehensive workflow for the automatic generation of functional simulators (a.k.a Instruction Set Simulators) from RTL, ensuring by construction the semantic consistency between the two abstraction levels.

Software and hardware acceleration of Neural Fields in autonomous robotics

Since 2020, Neural Radiance Fields, or NeRFs, have been the focus of intense interest in the scientific community for their ability to implicitly reconstruct 3D and synthesize new points of view of a scene from a limited set of images. Recent scientific advances have drastically improved initial performance (reduction in data requirements, memory needs and processing speed), paving the way for new uses of these networks, particularly in embedded applications, or for new purposes.
This thesis therefore focuses on the use of these networks for autonomous robotic navigation, with the embedded constraints involved: power consumption, limited computing and memorization hardware resources, etc. The navigation context will involve extending work already underway on incremental versions of these neural networks.
The student will be in charge of proposing and designing innovative algorithmic, software and hardware mechanisms enabling the execution of NeRFs in real time for autonomous robotic navigation.