Design and test of a PLL in FD-SOI 28nm technology

The goal of this PhD thesis is to design a Phase Locked Loop for generic use at 5 GHz. This PLL will also include a study regarding each building bloc sensitivity to radiation and thermal sensitivity regarding space environment. This is the main point of this PhD thesis because integrating a PLL in harsh environment requires an accurate knowledge of the circuit's parameters. The candidate will begin its work by analysing existing works on the FD-SOI technology (structure characteristics and impact on radiation hardening) to serve as a base for its work and design a Phase Locked Loop architecture. He will also study how to characterise each PLL building bloc variations in harsh environment (radiation and temperature).