Room temperature ferroelectric thin films are the key element of high density, low consumption nonvolatile memories. However, with the further miniaturization of the electronics devices beyond the Moore’s law, conventional ferroelectrics suffer great challenge arising from the critical thickness effect, where the ferroelectricity is unstable if the film thickness is reduced to nanometer or single atomic layer limit. Two-dimensional (2D) materials, thanks to their stable layered structure, saturate interfacial chemistry, weak interlayer couplings, and the benefit of preparing stable ultra-thin film at 2D limit, are promising for exploring 2D ferroelectricity and related device applications. So far, proof of concept demonstrating 2D ferroelectricity has predominantly utilized small flakes (less than a few hundred µm) mechanically exfoliated from a bulk crystal. In particular, atomically thin alpha (or gamma)-In2Se3 lamellar semiconductor preserves a ferroelectric character at 2D limit.
Given the imperative for wafer-scale electronics applications, there is a pressing need for large area growth of high quality 2D materials using bottom-up processes. The objective of this PhD project is to develop the growth of lamellar In2Se3 in its alpha or gamma phase crystal structures by chemical vapor phase epitaxy (MOCVD) on large silicon substrates (200 mm). The proof of concept of a ferroelectric memory cell will be performed by directly depositing a metal electrode on the surface of the 2D ferroelectric material without damaging it.

The miniaturization of the electronics components involves the development of new processes. Indeed, the 193nm immersion lithography alone does not permit anymore to achieve the dimensional requirements of the most advanced technological nodes (=10nm). Since the last 10 years, multi-patterning techniques have been developed to overcome the i193nm lithography limitations. Herein, we will study the « Self-Aligned Double Patterning » (SADP) technique that divides by two the initial pitch of the lithographical patterns. This technology relies on a conformal deposition of a dielectric film (spacer) over the initial patterns (mandrel). The spacers will be then used as a mask during the pattern transfer by plasma etching. The small targeted dimensions require a perfect control of the etching processes. However, the etching steps can damage the materials used herein leading to a dimension loss. One of the main challenge will be to control the etching steps and so the plasma-induced modification in order to satisfy the specifications (dimension, profile, material consumption, etch rate, uniformity…). Besides, the goal will be also to propose new SADP approaches allowing us to generate different type of patterns in order to produce planar FDSOI transistors, which is currently little reported in literature.

The challenges of this PhD ?
To develop innovative etching processes
To explore new couple of material (spacer/mandrel) and to propose an industrial integration flow that will be validated by electrical tests
To identify the technological obstacles and to propose solutions for overcoming them
To put in place a reliable characterization protocol in order to detect the physical and chemical modifications of the materials used and to accurately measure the final patterns’ dimensions

In recent years, CEA-LETI emerged as a leading force in the development of advanced microelectronic manufacturing processes. A key focus has been on wafer-to-wafer Cu/SiO2 hybrid bonding (HB) process, an emerging technology increasingly employed for producing compact, high performance and multifunctional devices. Before bonding, a crucial surface activation step is necessary to enhance the mechanical strength of the assembled structures. Different approaches have been developed, and the most used in the industry is N2-plasma activation. However, this process remains controversial due to undesirable effects, the formation of Cu nodules at the bonding interface between particularly electrical pads and the passivation of Cu pads with chemical complexes. These issues can significantly compromise the electric properties and reliability of devices. In collaboration with STMicroelectronics and IM2NP, this PhD aims at studying the impact of plasma activation on Cu/SiO2 HB integrations.