An increasing number of safety-critical systems now rely on artificial intelligence functions that must operate under strict energy constraints and in environments characterized by data scarcity and high uncertainty. However, conventional deterministic AI approaches provide only point estimates and lack principled uncertainty quantification, which can lead to unreliable or unsafe decisions in real-world deployment.

This PhD is positioned within the emerging field of Bayesian electronics, which aims to implement probabilistic inference directly in hardware by leveraging the intrinsic stochasticity of nanoscale devices to represent and manipulate probability distributions. While memristive devices have previously been explored for Bayesian inference, their limited endurance and high programming energy remain critical bottlenecks for on-chip learning.

The objective of this thesis is to investigate ferroelectric field-effect memory transistors (FeMFETs) as building blocks for hardware Bayesian neural networks. The work will involve characterizing and modeling the exploitable ferroelectric randomness for sampling and probabilistic weight updates, designing Bayesian neuron and synapse architectures based on FeMFETs, and evaluating their robustness, energy efficiency, and system-level performance for safety-critical inference under uncertainty.

As digital content demand surges, 6G systems face major challenges, particularly in developing power amplifiers for Sub-THz frequencies. These frequencies promise ultra-high data rates but push the limits of current silicon technology. In AI datacenters, optical communication between GPUs is a must to reduce the total energy usage, compared to classical wiring. The highest speed devices are then needed in photodetectors & lasers’ electrical drivers. InP-based Heterojunction Bipolar Transistors (HBTs) on large silicon substrates offer a promising solution, combining high-speed performance with minimal system losses. This technology comes with the challenges of integrating III-V layers with CMOS-compatible processes while allowing promising new device architectures, for both electrical parasitics reduction and self-heating management.
This PhD program aims to guide Leti’s III-V HBT on Si developments to optimize the device architecture and increase the RF performance.
In this program the student will:
Perform electrical characterization of various device geometries and technological splits through DC and RF measurements such as IV, thermal analysis, S-parameters and possibly Load-Pull.
Simulate key parasitics and new device architectures to understand device limitations
Collaborate closely with process engineers to link electrical results with fabrication choices and guide device optimization

This PhD topic offers a unique opportunity to enhance your skills in GaN power devices and develop cutting-edge architectures. You’ll work alongside a multidisciplinary team specializing in material engineering, characterization, device simulation, and electrical measurements. If you’re eager to innovate, expand your knowledge, and tackle state-of-the-art challenges, this position is a valuable asset to your career!
Vertical GaN power components are highly promising for applications beyond the kV range and are therefore extensively studied worldwide. Transistors with a 'trench MOSFET' architecture have been demonstrated in the state-of-the-art with very encouraging results. The gate stack of these devices is a crucial element as it directly impacts their on-state resistance, threshold voltage, and the control signal to be applied in a power converter. The proposed study will focus on developing innovative gate stacks that can withstand high gate voltages while maintaining state-of-the-art threshold voltage and channel mobility with minimal gate dielectric trapping. The work will involve studying the impact of process parameters on electrical characteristics. Special attention will be given to optimizing the gate geometry through TCAD simulations to study how its shape impacts on-state and breakdown. Identified improvements will be integrated to the devices fabricated on our 200mm GaN power devices line. The work will take place within the power devices lab and will be supported by several ongoing projects.

The rapid expansion of AI and cloud computing has placed unprecedented demands on data center infrastructure, where energy efficiency is now a defining constraint. Despite their potential, many power systems still rely on silicon-based devices, which suffer from inherent efficiency limitations that result in significant energy losses. GaN HEMTs, with their superior electron mobility and high breakdown voltage, represent a compelling alternative, capable of achieving far higher efficiencies in power conversion. However, their broader adoption is constrained by reliability challenges, particularly those arising from charge trapping mechanisms that degrade device performance over time.
In this PhD project, you will delve into the fundamental dynamics of charge carriers in GaN HEMTs, focusing on the physical origins of on-resistance and threshold voltage drifts—key indicators of device instability. By systematically analyzing the electrical behavior of these transistors under various operating conditions, you will uncover the mechanisms behind their degradation and identify pathways to enhance their robustness. Your findings will directly inform the optimization of device architectures, enabling the development of more efficient and reliable power electronics that can meet the demands of modern data centers and beyond.
You will be part of a multidisciplinary research team at CEA-Leti, collaborating with experts in semiconductor material engineering, device simulation, and electrical characterization. This environment will provide you with a comprehensive skill set, spanning process engineering, advanced electrical testing, and TCAD simulations, This position will not only expand your expertise but also position you at the forefront of a field with global impact. By contributing to the advancement of GaN HEMTs, you will play a key role in shaping the future of power electronics—where innovation directly translates into sustainable technological solutions.

The proposed PhD work lies within the exploration of new supercapacitor and hybrid energy storage technologies, aiming to combine miniaturization, high power density, and CMOS process compatibility. The hosting laboratory (LTEI/DCOS/LCRE) has recognized expertise in thin-film integration and dielectric material engineering, offering unique opportunities to investigate ferroelectric (FE) and antiferroelectric (AFE) behaviors in doped hafnium oxide (HfO2).

The thesis will focus on the experimental investigation and physical modeling of thin-film HfO2-based capacitors, intentionally doped to exhibit ferroelectric or antiferroelectric properties depending on the composition and deposition conditions (for instance, through ZrO2 or SiO2 doping). Such materials are particularly attractive for realizing devices that combine non-volatile memory and energy storage functions on a single CMOS-compatible platform, enabling ultra-low-power autonomous systems such as edge computing architectures, environmental sensors, and smart connected objects.

The research will involve the fabrication and characterization of metal–insulator–metal (MIM) capacitors based on doped HfO2 integrated on silicon substrates. Systematic electrical measurements—including current–voltage (I–V) and polarization–electric field (P–E) characterizations—will be carried out under various frequencies, amplitudes, and cycling conditions to investigate the relaxation mechanisms of FE and AFE domains. Analysis of minor hysteresis loops will provide access to the distribution of activation energies and enable the modeling of domain relaxation dynamics. A physical model will be developed or refined to describe FE/AFE transitions under cyclic electrical excitation, incorporating effects such as charge trapping, mechanical stress, and domain nucleation kinetics.

The overall objective is to optimize the recoverable energy density and the energy conversion efficiency of these capacitors, while establishing design guidelines for compact, efficient, and silicon-integrable energy storage devices. The insights gained from this work will contribute to a deeper understanding of the dynamic mechanisms governing FE/AFE behavior in doped HfO2, with potential impact on ferroelectric memories, energy-harvesting devices, and low-power neuromorphic architectures.