Design of a misalignment-robust, high-frequency GaN-based inductive power transmission system

The LAIC laboratory of CEA-LETI's Systems Department in Grenoble is specialized in the development of innovative electronic and mechatronic systems, taking into account challenges linked to energy recovery / management / transmission and sensor integration in a variety of environments. As part of the development of its R&D activities, the LAIC is offering a PhD thesis on wireless power transmission using GaN-based resonant inductive coupling.

Wireless power transmission technologies are booming, with applications in space, consumer electronics, medical, automotive and defense sectors. Power transmission technology using resonant inductive coupling appears to be the most promising in terms of near-field efficiency.

The proposed thesis will follow the development of a system including a fixed-coupling electromagnetic coupler and HF electronics based on a GaN transistor-based class-E topology. In this context, the aim of the thesis is to develop a system robust to coupler coil misalignment. The aim is to study, develop and test the performance of a new coupler and an adaptive drive electronics. The candidate will be required to develop analytical and numerical models to optimize the electronics, compare the performance of existing systems in the literature, and propose, develop and test the performance of innovative GaN-based topologies ensuring good robustness to electromagnetic coupling variation.

A multi-disciplinary profile with a focus on power electronics and physics is required for this thesis. In addition to a solid theoretical ground and strong simulation skills, the PhD student will need to be able to work as part of a team, with an aptitude for experimentation and an attraction for practical applications.

3D assembly of GaN power devices

The increase in electrical power density in everyday uses is the result of technological developments including materials and components. The first element to address is the use of a semiconductor material suitable for strong integration and capable of managing high power densities. Since the 2010s, wide bandgap semiconductors such as SiC or GaN have emerged in several applications and are causing a revolution in power electronics design, notably with an increase in the operating frequency and specific power of converters. Concerning Galium nitride (GaN), the increase in switching frequency was made possible thanks to the HEMT (High Electron Mobility Transistor).
The idea of ??this PhD topic is to work on a HEMT GaN cell assembly. The work will involve the an assembly of two components through a common electrode on their backsides in order, making it possible to reduce parasitic inductances and increase the operating frequency. The work will be based on simulation tools such as COMSOL and Synopsys. The thesis will be in collaboration with the GEEPS laboratory at CentraleSupelec and the University of Paris-Saclay.

Privacy-preserving federated learning over vertically partitioned data from heterogeneous participants

Federated learning enables multiple participants to collaboratively train a global model, without sharing their data, but only model parameters are exchanged between the participants and the server. In vertical federated learning (VFL), datasets of the participants share similar samples, but have different features. For instance, companies and institutions from different fields own data with different features of overlapping samples collaborate to solve a machine learning task. Though data are private, VFL remains vulnerable to attacks such as label and feature inference attacks. Various privacy measures (e.g., differential privacy, homomorphic encryption) have been investigated to prevent privacy leakage. Choosing the appropriate measures is a challenging task as it depends on the VLF architecture and the desired level of privacy (e.g., local models, intermediate results, learned models). The variability of each participant’s system can also result in high latency and asynchronous updates, affecting training efficiency and model effectiveness.

The aim of this thesis is to propose methods to enable privacy-preserving VFL, taking into account the heterogeneity of the participants. First, the candidate will study the architectures of VFL models and the privacy measures to propose privacy-preserving protocols for VFL. Second, the candidate will investigate the impacts of the heterogeneity of the participants’ system such as computation and communication resources to devise solutions to render the VFL protocols robust to such heterogeneity. Third, the trade-offs among effectiveness, privacy, and efficiency in VFL will be explored to propose a practical framework for adjusting the protocols according to the requirements of a given machine learning problem.

Advanced fully-depleted Silicon-on-insulator devices for Radio-Frequency applications

The PhD will be performed in the NEXTGEN project aimed at developing the next generation of Silicon-on-insulator devices. Our laboratory is driving the development of the RF active devices: this is a great opportunity to carry out fundamental research using state-of-the art processing equipment and characterization instruments while working in close collaboration with our industrial partners.

you will expected to engage in tasks encompassing:
- perform back-of the-envelope estimation of device properties and assess performace impact of technological choices
- Perform and/or analyze TCAD simulations to gain insight in the RF device behaviour
- data-mining on engineering measurements: grasp the relevant information and identify trends or correlations
- perform extensive periods of time in the lab to conduct or participate in on-wafer RF characterization champaign.
Based on you profile or expectations, above tasks may be dynamically rebalanced during the thesis.

Development and characterization of low temperature Cu-dielectric hybrid bonding

Cu-dielectric hybrid bonding is a technology that enables the assembly of components with very fine interconnection pitch, opening the path to new integrations for advanced applications such as High Performance Computing, Smart Imagers,… Leti has been engaged for more than 10 years in the development of this technology, in partnership with various industries and academies, to master smaller and smaller connection pitches (< 1µm), or to evaluate new techniques such as ‘die-to-wafer’ self-assembly. In this context, low temperature hybrid bonding would allow new integration routes notably for heterogeneous systems (III-V on CMOS,…) or for thermally sensitive components (colored resins, non-volatile memories,…).

The objective of this thesis is to develop and characterize Cu-dielectric hybrid assemblies performed at low temperature, from ambient to 250°C. A first part of the thesis will aim at identifying the dielectric materials that are relevant for the hybrid bonding technology (SiN, SiON, SiCN, …). The critical properties of these materials (permittivity, hygroscopy,…) will be measured and compared to the reference high temperature SiO2. In a second part, the selected dielectrics will be integrated in the ‘wafer-to-wafer’ hybrid bonding technology and each process step (damascene level, surface preparation, direct bonding) will be adapted as needed. The third part of the thesis will be dedicated to the electrical characterization and reliability tests of the obtained low temperature hybrid bonding.

Stocastic integrated power supplies based on emerging components

The widespread utilization of connected devices that process sensitive information necessitates the creation of new secure systems. The prevalent attack, referred to as power side-channel, involves the retrieval of encryption key information by analyzing the power consumption of the system. Integrating the system with its power supply management blocks can conceal the consumption of sensitive blocks, especially by utilizing various techniques to introduce randomized variations during power transfer. The CEA has wide experience in the design and testing of secure integrated circuits and it is exploring a new approach to DC-DC conversion that uses emerging devices available at CEA-Léti.
The work of the PhD researcher will be the following:
- Specification of integrated power supplies using switched-capacitor architecture.
- Study the circuit using emerging components and evaluate the improvement of its robustness against side channel attacks.
- Design of the integrated power supply in silicon technology.
- Performance and security characterization of the designed blocks and security primitives in
their whole.
The division of labor is 10% advanced study, 20% system architecture, 50% circuit design, 20% experimental measurement.

Laser Fault Injection Physical Modelling in FD-SOI technologies: toward security at standard cells level on FD-SOI 10 nm node

The cybersecurity of our infrastructures is at the very heart in the digital transition on-going, and security must be ensured throughout the entire chain. At the root of trust lies the hardware, integrated circuits providing essential functions for the integrity, confidentiality and availability of processed information.
But hardware is vulnerable to physical attacks, and defence has to be organised. Among these attacks, some are more tightly coupled to the physical characteristics of the silicon technologies. An attack using a pulsed laser in the near infrared is one of them and is the most powerful in terms of accuracy and repeatability. Components must therefore be protected against this threat.
As the FD-SOI is now widely deployed in embedded systems (health, automotive, connectivity, banking, smart industry, identity, etc.) where security is required. FD-SOI technologies have promising security properties as being studied as less sensitive to a laser fault attack. But while the effect of a laser fault attack in traditional bulk technologies is well handled, deeper studies on the sensitivity of FD-SOI technologies has to be done in order to reach a comprehensive model. Indeed, the path to security in hardware comes with the modelling of the vulnerabilities, at the transistor level and extend it up to the standard cells level (inverter, NAND, NOR, Flip-Flop) and SRAM. First a TCAD simulation will be used for a deeper investigation on the effect of a laser pulse on a FD-SOI transistor. A compact model of an FD-SOI transistor under laser pulse will be deduced from this physical modelling phase. This compact model will then be injected into various standard cell designs, for two different objectives: a/ to bring the modelling of the effect of a laser shot to the level of standard cell design (where the analog behaviour of a photocurrent becomes digital) b/ to propose standard cell designs in FD-SOI 10nm technology, intrinsically secure against laser pulse injection. Experimental data (existing and generated by the PhD student) will be used to validate the models at different stages (transistor, standard cells and more complex circuits on ASIC).
Ce sujet de thèse est interdisciplinaire, entre conception microélectronique, simulation TCAD et simulation SPICE, tests de sécurité des systèmes embarqués. Le candidat sera en contact/encadré avec deux équipes de recherche; conception microélectronique , simulation TCAD et sécurité des systèmes embarqués.


Medium temperature PEMFC: impact of the drying processes of catalyst layers on their microstructure and performance

- The Proton Exchange Membrane Fuel Cell (PEMFC, using H2 and air as fuels) is a relevant solution for the production of low-carbon electrical energy. However, it is necessary to further improve its performance and durability, and reduce its cost.
- In this spirit, the national French project PEMFC95 aims at developing and characterizing PEMFC materials able to operate sustainably at 95°C (standard is 80°C) and thus more suitable and attractive for Heavy-Duty application (buses, trucks, trains…). It is supported by the French ‘Programme et Equipements Prioritaires de Recherche sur l’hydrogène décarboné’ (PEPR-H2).
- The component considered in this thesis is the catalyst layer (CL) which is a mixture of Pt/C (platinum onto carbon particles), H+ conductive ionomer, and solvents. The optimization of the CL in terms of spatial distribution of Pt/C, ionomer and pores is crucial for improving performance and durability. This is directly linked to the ink formulation and to the manufacturing process used to produce the CL. Nevertheless, the relation between the CL manufacturing process and parameters, its structure and components’ distribution, and the performance and durability of the PEMFC, is still an open question. The aim of your Ph.D. thesis is to progress on this, focusing on the drying step of the bar coater manufacturing process.
- You will contribute to the PEMFC95 project thanks to your scientific/technological developments to understand the impact of the drying process and parameters on the microstructure of CL and make the link with the performance and durability of PEMFC.
- You will have interactions and meetings with the partners of the project and with CNRS/IMFT (Toulouse), specialist of transport phenomenon in porous media.
You will be hired by CEA-Grenoble and work with permanent and non-permanent staff in the laboratory, (male and female) engineers and technicians, to discuss your ideas, perform your experiments and analyze the data. You will be managed by Joël Pauchet as your thesis director, specialist of porous media and their modeling for PEMFC, and Christine Nayoze-Coynel for her knowledge on the CL and MEA manufacturing.

More information are accessible in the attached file and/or Under request.

Environmental applications of the metrological study of photonuclear reactions on light elements.

Through a thesis and a project funded by the LNE, the LNHB is developing a prototype for the detection of illicit materials using the active photon interrogation method, based on the spectrometry of photoneutrons emitted by targets irradiated by a linear electron accelerator. This new thesis topic involves studying photonuclear reactions on light elements for environmental applications, primarily through a better understanding of photoneutrons, secondary neutrons and cosmogenic radionuclide production rates in the atmosphere during terrestrial gamma ray flashes associated with thunderstorms or gamma-ray bursts of cosmic origin. The LNHB-MD's unique experimental facility will be use to obtain basic nuclear data, such as the angular and energy distributions of photoneutrons emitted by light elements, and to characterize activation products. The data collected will be use to improve the description of photonuclear processes for light elements in Monte-Carlo codes, and to estimate their influence on measurable quantities through simulation codes for environmental phenomena. The same methodology can be apply to the study of photonuclear reactions in rocks - composed mainly of light elements - following irradiation by high-energy photons of natural or artificial origin.

Design and construction of a snubber circuits associated with a power transistors in order to reduce disturbances during fast switching.

The thesis topic is aligned with the European Common Interest Project IPCEI ME/CT, which aims to enhance the value of the European semiconductor sector. It particularly investigates protection systems for direct current (DC) electrical networks against power overloads, short circuits, and electric arc incidents. These complex systems rely on power transistors to manage controlled disconnection of the electrical network, incorporating either separate functions or combined functions with a DC-DC converter.

Despite the abundant literature on the subject, it showcases a variety of approaches and configurations depending on the DC voltage and power levels involved. This project focuses on the activation of DC lines under severe conditions, initially at 400V (low-voltage DC, LVDC) and subsequently at 800V (medium-voltage DC, MVDC).

In the LVDC context, the emergence of GaN HEMT transistors (Gallium Nitride, with a breakdown voltage greater than 650V) has enabled the study of how well these components perform in line disconnection tasks. The rapid switching of the transistor necessitates precise control of the switching trajectory to ensure that the transistor operates within the safety limits specified by the manufacturer. Typically, this involves a snubber circuit for switching assistance. If an overvoltage cannot be avoided, a clamping device is added in parallel to the transistor. Experimental validation of such setups is quite challenging, especially when transistors are used in series or parallel, which motivates the development of alternatives that do not rely on a snubber circuit. However, due to the relative fragility of GaN transistors, this approach is not optimal.

Therefore, the project looks at integrating a switching assistance solution within the GaN transistor package. The production of the transistors and snubbers will utilize the facilities and techniques of the CEA-Leti cleanrooms, with microelectronic manufacturing processes optimized to allow their integration with silicon trench capacities, enabling co-integration with GaN transistors. The components will be assembled after being encapsulated.

Switching tests will initially be conducted within an inverter arm to assess various snubber circuit designs, switching frequencies, speeds, and temperatures. An ultra-fast metrological approach will be developed alongside the transistor design to enable measurements without compromising functionality.

In a later phase, the most promising solutions will also be validated within a back-to-back setup, in the particularly challenging case of opening an inductive DC line.