Integrated material–process–device co-optimization for the design of high-performance RF transistors on advanced nanometer technologies
This PhD research focuses on the integrated co-optimization of materials, fabrication processes and device architectures to enable high-performance RF transistors on advanced nanometer-scale technologies. The work aims to understand and improve key RF figures of merit—such as transit frequency, maximum oscillation frequency, noise behaviour and linearity—by establishing clear links between material choices, process innovations and transistor design.
The project combines experimental development, structural and electrical characterization, and advanced TCAD simulations to analyse the strengths and limitations of different integration schemes, including FD-SOI and emerging 3D architectures such as GAA and CFET. Particular attention will be given to the engineering of optimized spacers, gate stacks, junction placement and epitaxial source/drain materials in order to minimize parasitic effects and enhance RF efficiency.
By comparing planar and 3D device platforms within a unified modelling and characterization framework, the thesis aims to provide technology guidelines for future generations of energy-efficient RF transistors targeting applications in 5G/6G communications, automotive radar and low-power IoT systems.
Understanding the origin of charge noise in quantum devices
Thanks to strong collaborations between teams from several research institutes and the cleanroom facilities at CEA-LETI, Grenoble has been a pioneer in the development of spin qubit devices as a platform for quantum computing. The lifetime of these spin qubits is highly sensitive to fluctuations in the qubit's electrical environment, known as charge noise. Charge noise in spin qubit devices potentially originates from trapping/detrapping events within the amorphous and defective materials (e.g., SiO2, Si3N4). This PhD project aims to better understand the origin of this noise through numerical simulations, and guide the development of quantum devices towards lower noise levels and higher quality qubits.
The goal of this PhD position is to improve the understanding of noise in spin qubit devices through multi-scale simulations going from the atomistic to the device level. The PhD candidate will use codes developed at CEA for the numerical modeling of spin qubits and will leverage supercomputing facilities to perform the simulations. Depending on the candidate’s profile and interests, code development may be considered. The work will also involve collaborations with experimentalists to validate simulation methods and to aid in the interpretation of experimental results.
Instrumented PCB for predictive maintenance
The manufacturing of electronic equipment, and more specifically Printed Circuit Boards (PCBs), represents a significant share of the environmental impact of digital technologies, which must be minimized. Within a circular economy approach, the development of monitoring and diagnostic tools for assessing the health status of these boards could feed into the product’s digital passport and facilitate their reuse in a second life. In a preventive and prescriptive maintenance perspective, such tools could extend their lifespan by avoiding unnecessary periodic replacement in applications where reliability is a priority, as well as adapting their usage to prevent premature deterioration.
This PhD proposes to explore innovative instrumentation of PCBs using ‘virtual’ sensors, advanced estimators powered by measurement modalities (such as piezoelectric, ultrasonic, etc.) that could be integrated directly within the PCBs. The objective is to develop methods for monitoring the health status of the boards, both mechanically (fatigue, stresses, deformations) and electronically.
A first step will consist of conducting a state-of-the-art review and simulations to select the relevant sensors, define the quantities to be measured, and optimize their placement. Multi-physics modeling and model reduction will then make it possible to link the data to PCB integrity indicators characterizing its health status. The approach will combine numerical modeling, experimental validations, and multiparametric optimization methods.
Electron beam probing of integrated circuits
The security of numerical systems relies on cryptographic chains of trust starting from the hardware up to end-user applications. The root of chain of trust is called a “root of trust” and takes the form a dedicated Integrated Circuit (IC), which stores and manipulates secrets. Thanks to countermeasures, those secrets are kept safe from extraction and tampering from attackers.
Scanning Electron Microscope (SEM) probing is a well-known technique in failure analysis that allows extracting such sensitive information. Indeed, thanks to a phenomenon known as voltage contrast, SEM probing allows reading levels of transistors or metal lines. This technique was widely used in the 90s on ICs frontside, but progressively became impractical with the advance of manufacturing technologies, in particular the increasing number of metal layers. Recent research work (2023) showed that SEM-based probing was possible from the backside of the IC instead of frontside. The experiments were carried-out on a quite old manufacturing technology (135 µm). Therefore, it is now essential to characterize this threat on recent technologies, as it could compromise future root of trusts and the whole chains of trust build on top of them.
The first challenge of this PhD is to build a reliable sample preparation process allowing backside access to active regions while maintaining the device functional. The second challenge is to characterize the voltage contrast phenomenon and instrument the SEM for probing active areas. Once the technique will be mature, we will compare the effect of the manufacturing technology against those threats. The FD-SOI will be specifically analyzed for potential intrinsic benefits against SEM probing.
Development of multiplexed photon sources for quantum technologies
Quantum information technologies offers several promises in domains such as computation or secured communications. Because of their robustness against decoherence, photonic qubits are particularly interesting for quantum communications applications, even at room temperature. They also offers an alternative to other qubits technologies for quantum computing. For the large-scale deployment of those applications, it is necessary to have cheap, compact and scalable devices. To reach this goal, silicon photonics platform is attractive. It allows implementing key components such as generation, manipulation and detection of photonic qubits. On the silicon platform, the photonic qubits are generated by pair through non linear process. has several benefits, such as working at room temperature, the ability to generate heralded single photon, or undistiguishable photons with spatially distinct sources.
The goal of this thésis is to work on the development, the fabrication monitoring, and the characterization in the laboratory of multiplexed photon sources on silicon chips to overcome the limits in the process of photon generation with one source. In order to achieve a full integration on chip, it is also essential to properly filter unwanted light in order to keep only the photons that are of interest. As a consequence you will also focus on the development of intgrated filters with high rejection rate.
Injection-Locked Oscillators based Liquid Neural Networks for Generative Edge Intelligence
This PhD aims to design analog liquid neural networks for generative edge intelligence. Current neuromorphic architectures, although more efficient through in-memory computing, remain limited by their extreme parameter density and interconnection complexity, making their hardware implementation costly and difficult to scale. The Liquid Neural Networks (LNN), introduced by MIT at the algorithmic level, represent a breakthrough: continuous-time dynamic neurons capable of adjusting their internal time constants according to the input signal, thereby drastically reducing the number of required parameters.
The goal of this PhD is to translate LNN algorithms into circuit-level implementations, by developing ultra-low power time-mode cells based on oscillators that reproduce liquid dynamics, and interconnecting them into a stable, recurrent architecture to target generative AI tasks. A silicon demonstrator will be designed and validated, paving the way for a new generation of liquid neuromorphic systems for Edge AI.
Analysis and design of dispersion-engineered impedance surfaces
Dispersion engineering (DE) refers to the control of how electromagnetic waves propagate in a structure by shaping the relationship between frequency and phase velocity. Using artificially engineered materials and surfaces, this relationship can be tailored to achieve non-conventional propagation behaviors, enabling precise control of dispersive effects in the system. In antenna design, dispersion engineering can enhance several key aspects of radiation performance, including gain bandwidth, beam-scanning accuracy, and in general the reduction of distortions that arise when the operating frequency changes. It can also enable additional functionalities, such as multiband operation or multifocal behavior in lens- and reflector-based antennas.
This thesis aims to investigate the underlying physics governing the control of phase and group velocities in two-dimensional artificial surfaces with frequency-dependent effective impedance properties. A particular emphasis will be placed on spatially fed architectures, such as transmitarrays and reflectarrays, where dispersion plays a crucial role. The objective is to derive analytical formulations within simultaneously control of both group and phase delay, develop general models, and assess the fundamental limitations of such systems in radiation performance. This work is especially relevant for high-gain antenna architectures, where the state of the art remains limited. Current dispersion-engineered designs are mostly narrowband, and no compact high-gain solution (> 35 dBi) has yet overcome dispersion-induced degradations, which lead to gain drop and beam squint.
The student will develop theoretical and numerical tools, investigate new concepts of periodic unit cells for the impedance surfaces, and design advanced antenna architectures exploiting principles such as true-time delay, shared-aperture multiband operation, or near-field focsuing with minimized chromatic aberrations. The project will also explore alternative fabrication technologies to surpass the constraints of standard PCB processes and unlock new dispersion capabilities.
Optically Pumped Magnetometers based on helium-3
The laboratory, reknown for its expertise in high-resolution and high-precision magnetic measurements, has been developing and providing for several decades successive generations of optically pumped helium-4 magnetometers. These instruments serve as reference sensors aboard the ESA Swarm mission satellites launched in late 2013, and will also equip the forthcoming NanoMagSat mission, scheduled to launch from the end of 2027 onward.
In an effort to diversify its activities and to address emerging applications involving autonomous or “deploy-and-forget” sensors, where power consumption constraints are particularly demanding, the laboratory now aims to develop a new magnetometer technology based on helium-3 atoms as the sensitive medium. The lifetime of the helium-3 atomic state used for magnetic field measurement is significantly longer than that of the equivalent helium-4 state. This property enables a substantial reduction in optical pumping requirements, thereby offering the prospect of improved energy efficiency and power consumption.
The objective of this research is to advance the Technology Readiness Level (TRL) of this helium-3-based magnetometer architecture, with the ultimate goal of realizing an instrument that combines outstanding metrological performance with exceptional energy frugality, suited to these highly specific and constrained applications.
Accordingly, the purpose of this PhD work will be to design, implement, and experimentally evaluate a helium-3 magnetometer architecture capable of fulfilling these performance and efficiency objectives.
Topologic optimization of µLED's optical performance
The performance of micro-LEDs (µLEDs) is crucial for micro-displays, a field of expertise at the LITE laboratory within CEA-LETI. However, simulating these components is complex and computationally expensive due to the incoherent nature of light sources and the involved geometries. This limits the ability to effectively explore multi-parameter design spaces.
This thesis proposes to develop an innovative finite element method to accelerate simulations and enable the use of topological optimization. The goal is to produce non-intuitive designs that maximize performance while respecting industrial constraints.
The work is divided into three phases:
- Develop a fast and reliable simulation method by incorporating appropriate physical approximations for incoherent sources and significantly reducing computation times.
- Design a robust topological optimization framework that includes fabrication constraints to generate immediately realizable designs.
- Realize such a metasurface on an existing shortloop in the laboratory. This part is optional and will be tackled only if we manage to seize an Opportunity to finance the prototype, via the inclusion of the thésis inside the "metasurface
topics" of european or IPCEI projets in the lab .
The expected results include optimized designs for micro-displays with enhanced performance and a methodology that can be applied to other photonic devices and used by other laboratories from DOPT.
Modeling and characterization of CFET transistors for enhanced electrical performance
Complementary Field Effect Transistors (CFETs) represent a new generation of vertically stacked CMOS devices, offering a promising path to continue transistor miniaturization and to meet the requirements of high-performance computing.
The objective of this PhD work is to study and optimize the strain engineering of the transistor channel in order to enhance carrier mobility and improve the overall electrical performance of CFET devices. The work will combine numerical modeling of technological processes using finite element methods with experimental characterization of crystalline deformation through transmission electron microscopy coupled with precession electron diffraction (TEM-PED).
The modeling activity will focus on predicting strain distributions and their impact on electrical properties, while accurately accounting for the complexity of the technological stacks and critical fabrication steps such as epitaxy. In parallel, the experimental work will aim to quantify strain fields using TEM-PED and to compare these results with simulation outputs.
This research will contribute to the development of dedicated modeling tools and advanced characterization methodologies adapted to CFET architectures, with the goal of improving spatial resolution, measurement reproducibility, and the overall understanding of strain mechanisms in next-generation transistors.