Multi-scale modeling of the electromagnetic quantum dot environment
In the near future, emerging quantum information technologies are expected to lead to global breakthroughs in high performance computing and secure communication. Among semiconductor approaches, silicon-based spin quantum bits (qubits) are promising thanks to their compactness featuring long coherence time, high fidelity and fast qubit rotation [Maurand2016], [Meunier2019]. A main challenge is now to achieve individual qubit control inside qubit arrays.
Qubit array constitutes a compact open system, where each qubit cannot be considered as isolated since it depends on the neighboring qubit placement, their interconnection network and the back-end-line stack. The main goal of this post-doctoral position is to develop various implementation of spin control on 2D qubit array using multi-scale electromagnetic (EM) simulation ranging from nanometric single qubit up to millimetric interconnect network.
The candidate will i) characterize radio-frequency (RF) test structures at cryogenic temperature using state-of-the-art equipment and compare results with dedicated EM simulations, ii) evaluate the efficiency of spin control and allow multi-scale optimization from single to qubit arrays [Niquet2020], iii) integrate RF spin microwave control for 2D qubit array using CEA-LETI silicon technologies.
The candidate need to have a good RF and microelectronic background and experience in EM simulation, and/or design of RF test structures and RF characterization. This work takes place in a dynamic tripartite collaborative project between CEA-LETI, CEA-IRIG and CNRS-Institut Néel (ERC “Qucube”).
Non-volatile asynchronous magnetic SRAM design
In the applicative context of sensor nodes as in Internet of things (IoT) and for Cyber Physical Systems (CPS), normally-off systems are mainly in a sleeping state while waiting events such as timer alarms, sensor threshold crossing, RF or also energetic environment variations to wake up. To reduce power consumption or due to missing energy, the system may power off most of its components while sleeping. To maintain coherent information in memory, we aim at developing an embedded non-volatile memory component. Magnetic technologies are promising candidates to reach both low power consumption and high speed. Moreover, due to transient behavior, switching from sleeping to running state back and forth, asynchronous logic is a natural candidate for digital logic implementation. The position is thus targeting the design of an asynchronous magnetic SRAM in a 28nm technology process. The memory component will be developed down to layout view in order to precisely characterize power and timing performances and allow integration with an asynchronous processor. Designing such a component beyond current state of the art will allow substantial breakthrough in the field of autonomous systems.
Modeling of trapping and vertical leakage effects in GaN epitaxial substrates on Si
State of the art: Understanding and modeling vertical leakage currents and trapping effects in GaN substrates on Si are among the crucial subjects of studies aimed at improving the properties of GaN power components : current collapse and Vth instabilities reductions, reduction of the leakage current in the OFF state.
Many universities [Longobardi et al. ISPSD 2017 / Uren et al. IEEE TED 2018 / Lu et al. IEEE TED 2018] and industrials [Moens et al. ISPSD 2017] are trying to model vertical leakages but until now, no clear mechanism has emerged from this work to model them correctly over the entire range of voltage and temperatures targeted. In addition, modeling the effects of traps in the epitaxy is necessary for the establishment of a a robust and predictive TCAD model of device.
For LETI, the strategic interest of such a work is twofold: 1) Understanding and reducing the effects of traps in the epitaxy impacting the functioning of GaN devices on Si (current collapse, Vth instabilities…) 2) Reaching the leakage specifications @ 650V necessary for industrial applications.
The candidate will have to take charge in parallel of the electrical characterizations and the development of TCAD models:
A) Advanced electrical characterizations (I (V), I (t), substrate ramping, C (V)) as a function of temperature and illumination on epitaxial substrates or directly on finite components (HEMT, Diodes, TLM )
B) Establishment of a robust TCAD model integrating the different layers of the epitaxy in order to understand the effects of device instabilities (dynamic Vth, dynamic Ron, BTI)
C) Modeling of vertical conduction in epitaxy with the aim of reducing leakage currents at 650V
Finally, the candidate must be proactive in improving the different parts of the substrate
Simulation and electrical characterization of an innovative logic/memory CUBE for In-Memory-Computing
For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items. Things will change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. At LETI, we will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory.
The post-doc will perform electrical characterizations of CMOS transistors and Resistive RAMs in order to calibrate models and run TCAD/spice simulations to drive the technology developments and enable the circuit designs.
FDSOI technology scaling beyond 10nm node
FDSOI (Fully-Depleted Silicon On Insulator) is acknowledged as a promising technology to meet the requirements of emerging mobile, Internet Of Things (IOT), and RF applications for scaled technological nodes [1]. Leti is a pioneer in FDSOI technology, enabling innovative solutions to support industrial partners.
Scaling of FDSOI technology beyond 10nm node offers solid perspectives in terms of SoC and RF technologies improvement. Though from a technological point of view, it becomes challenging because of thin channel thickness scaling limitation around 5nm to maintain both good mobility and variability. Thus, introduction of innovative technological boosters such as strain modules, alternative gate process, parasitics optimization, according to design rules and applications, become mandatory [2].
The viability of these new concepts should be validated first by TCAD simulations and then implemented on our 300mm FDSOI platform.
This subject is in line with the recent LETI strategy announcement and investments to develop new technological prototypes for innovative technology beyond 28nm [3].
The candidate will be in charge to perform TCAD simulations, to define experiment and to manage them until the electrical characterization. The TCAD simulations will be performed in close collaboration with the TCAD team. The integration will be done in the LETI clean room in collaboration with the process and integration team. Candidate with out-of-the-BOX thinking, autonomy, and ability to work in team is mandatory.
[1] 22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications, R. Carter et al, IEEE IEDM 2016.
[2] UTBB FDSOI scaling enablers for the 10nm node, L. Grenouillet et al, IEEE S3S 2013.
[3]https://www.usinenouvelle.com/article/le-leti-investit-120-millions-d-euros-dans-sa-salle-blanche-pour-preparer-les-prochaines-innovations-dans-les-puces.
Design for reliability for digital circuits
Flash memories are a key enabler for high-temperature applications such as data acquisition and engine control in aerospace, automotive and drilling industries. Unfortunately, the retention time of flash memories is very sensitive to high temperatures. Even at relatively moderated temperatures, flash memories may be affected by retention-related problems especially if they are set to store more than one bit per cell. This impact can be mitigated by periodically refreshing the stored data. The problem is that, in the presence of a variable operating temperature that could be due to variable environmental and workload conditions, a fixed data-refresh frequency may become disproportionately large with a subsequent impact on response time and cycling endurance.
The first objective of this project is to implement a data-refresh method based on a specially designed counter that is able to (a) track the evolution of the temperature and its impact on the data retention time of Flash memory blocks, (b) trigger warnings against potential retention time hazards and (c) provide timestamps.
The second objective is to find the distribution law that gives the evolution of the number of data retention errors in time. The goal is to implement a methodology able to infer the remaining retention time of flash memory pages based on their data retention age, i.e., the elapsed time since data was stored, and the number of retention and non-retention errors.
The publication of the scientific results in high-ranked conferences and journals is major project objective.
Hardening energy efficient security features for the IoT in FDSOI 28nm technology
The security of the IoT connected objects must be energy efficient. But most of the work
around hardening by design show an additional cost, a multiplying factor of 2 to 5, on the
surface, performance, power and energy, which does not meet the constraints of the IoT.
Last 5 years research efforts on hardening have been guided by reducing silicon area or
power, which do not always imply a decrease in energy, predominant criterion in autonomous
connected objects. The postdoc topic addresses the hardening and energy consumption
optimization of the implementation of security functions (attack detection sensors,
cryptographic accelerator, random number generator, etc.) in 28nm FDSOI technology.
From the selection of existing security bricks, unhardened in FPGA technology, the postdoc
will explore hardening solutions at each step of the design flow in order to propose and
to validate, into a silicon demonstrator, the most energy efficient countermeasures that
guarantee a targeted security level.
To achieve those goals, the postdoc can rely on existing methodologies of design and of
security evaluation thanks to test benches and attack tools.
Study of substrate coupling in millimeter wireless circuits
The candidate will study substrate coupling in millimeter wireless circuit. He will demonstrate the influence of silicon substrate on millimeter circuit design
The first task will consist in establishing the state of the art of substrate reduction technics on millimeter chip. The influence between building blocks at layout level will be analyzed. Parasitic noise effects, frequency and power spurious will be studied with coupling substrate tool. Specifications for layout design in order to reduce spurious will be done, especially for power, analog and digital applications. A design methodology will be proposed with this results.
Development of a mechanical energy harvester based on a rotating machine architecture with permanent magnets
This Post-doc offer will be aimed at developing energy harvesters, and more especially electromagnetic energy harvesters with an operation mode close to the one of rotating machines with permanent magnets. The post-doc applicant will have a background in electrical engineering and an experience in rotating machines design, ideally, with permanent magnets.
The missions of the Post-doc applicant will be to:
1) Imagine and design small-scale innovative energy harvesters by exploiting the techniques used in rotating machines.
2) Model and optimize the devices
3) Characterize the systems
4) Participate to the industrialization process
Design / Technology Co-Optimization of SRAM and standard cells on stacked nanowires at the 5nm technology node
The post-doctoral position will focus on the layout of SRAM and standard cells dedicated to the 5nm node on stacked nanowires integrating a Direct Self-Assembly solution (DSA). He/she will use the SPICE model developed at LETI and interact with both model and process/integration teams to find the best layout for a set of cells.