3D sequential integration
3D integration is currently under great investigation because it offers a solution to keep increasing transistor density while relaxing the constraint on the transistor’s dimension and it eases the co integration of highly heterogeneous technologies compared to a planar scheme.
3D sequential integration offers the possibility of using the third-dimension potential: two stacked layers can be connected at the transistor scale. This contrasts with 3D parallel integration, which is limited to connecting blocks of a few thousand transistors. However, its implementation faces the challenge of being able to process a high performance top transistor at low temperature in order to preserve the bottom FET from any degradation, as the stacked FETs are fabricated sequentially.
Reliability of the copper (Cu) direct bonding interconnects for 3D integration
Copper direct bonding is one of the most promising approaches for 3-D integration. The process is mature as shown in the literrature for wafer to wafer (W2W) approach [1-3] but also in the case of a die to wafer one (D2W). However, its reliability is yet to be demonstrated even if the initial results from the PhD thesis of R. Taibi seem to be promising [4].
The purpose of this post-doc position will be first, to consolidate the results obtained by R. Taibi with the W2W approach and secondly, to study the reliability of the D2W approach from the electromigration and stress-induced voiding point of view.
The candidate will be responsible for all the reliability study, starting with the tests and the results’ analysis, failure analysis (optical, IR, SEM, FIB...), the determination of the degradation’s mechanisms.
1. Gueguen, P., et al. Copper direct bonding for 3D integration. in Interconnect Technology Conference, 2008. IITC 2008. International. 2008.
2. Taibi, R., et al. Full characterization of Cu/Cu direct bonding for 3D integration. in Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th. 2010.
3. Di Cioccio, L., et al., An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization. Journal of The Electrochemical Society, 2011. 158(6): p. 81-86.
4. Taibi, R., et al., Investigation of Stress Induced Voiding and Electromigration Phenomena on Direct Copper Bonding Interconnects for 3D Integration, in 2011 IEEE International Electron Devices Meeting (IEDM). 2011: Washington, DC.
Electrical Study of Conductive Bridge Random access Memory (CBRAM)
CBRAM memories are among the most promising technologies as alternative to Flash technologies which face strong problems of scaling. CBRAM have a capacitor-like stack, where a chalcogenide material is sandwiched between a silver anode and an inert cathode. Biasing the cell, silver ions diffuse in the chalcogenide matrix and reach the cathode where they reduce. A conductive bridge is formed between the electrodes causing a drop of resistance. Reversing the bias yields to a back-migration of silver, interrupting the conductive bridge. This kind of device can be operated at very low voltage (below 1 V) and can lead to extremely low power consumption.
The main objective of this postdoc position will be the electrical characterization aiming to a better comprehension of the physics involved in the device, with the final goal of a strong improvement in device characteristics, in particular concerning data retention. For this aim, in-depth characterization on particular features (i.e. conduction mode, failure mechanisms) will be performed, as much as possible linked to a first level of physical modelling linking current conduction and diffused ions in the matrix. The candidate will address both hardware & methodology issues, and particular attention will be devoted to pulsed measurements. Various process, geometries and architectures will be studied. A strong interaction with the specialists of materials characterizations (nano-characterization platform) will be promoted for a better physical knowledge of the structures.
Porous layer integration for advanced temporary substrates
Double transfer of thin single crystalline processed layer can be very interesting for all technologies that require front and back side engineering of the silicon active film. With the increase of the electronical system complexity, this alternative technology can offer new opportunities to miniaturize the semiconductor devices. To fulfill such requirements, a recent alternative technology was developed at the CEA-LETI, based on the use of porous silicon substrates [1]. This new technology will be of a great interest for 3D integration, back-side imager but also MEMS or photovoltaics applications. This technology should now be validated at a larger scale, and we need to focus on all involved mechanisms such as the porous silicon layer rupture.
In a first place, the applicant should comprehend the specification of porous materials in thin film configuration, including elaboration steps and distinctive properties of transferred porous layers. Subsequently he/she may need to interact with Leti’s technological experts to determine process improvements to be implemented to reach pre-established specifications of desired prototypes. In order to evaluate and recommend appropriate materials and equipments, he/she may need to extensively focus on the behaviour of porous material under specific stress conditions such as chemical, thermal or mechanical solicitations. The purpose is to ensure compliance to Smart Cut or Smart stacking technologies that involve amongst others processes molecular bonding technology.
Later, the effort should be focused on the development of a specific technology to induce the mechanical separation inside the buried porous silicon layer. One line of approach would be to trigger the mechanical separation by ultrasound solicitation. Understanding the mechanisms of the splitting and characterising the resulting structures are part of the expected work to be completed in this project.
[1] A-S.Stragier et al., JECS,158 (5) H595-H599 (2011)
Study of the thermo-mechanical strains in the HEMT AlGaN/GaN on silicon
Fabricating the HEMT AlGaN/GaN device is complex and leads to the formation of crystalline defects. These strains, in the GaN layer, leads to crackings in the GaN layer or leads to a delamination at the top interface. Moreover, these mechanical strains conjugated to thermal strains during device working, can lead to a degradation of the electrical performance of the device.
This heterogeneous assembly, involve a complex behaviour. The various materials used, react differently to the thermal-mechanical strains. The requested work is to study and to model the distortion of this structure, in order to evaluate the strains effects on the electrical performance on lateral and vertical devices.
Scalable digital architecture for Qubits control in Quantum computer
Scaling Quantum Processing Units (QPU) to hundreds of Qubits leads to profound changes in the Qubits matrix control: this control will be split between its cryogenic part and its room temperature counterpart outside the cryostat. Multiple constraints coming from the cryostat (thermal or mechanical constraints for example) or coming from Qubits properties (number of Qubits, topology, fidelity, etc…) can affect architectural choices. Examples of these choices include Qubits control (digital/analog), instruction set, measurement storage, operation parallelism or communication between the different accelerator parts for example. This postdoctoral research will focused on defining a mid- (100 to 1,000 Qubits) and long-term (more than 10,000 Qubits) architecture of Qubits control at room temperature by starting from existing QPU middlewares (IBM QISKIT for example) and by taking into account specific constraints of the QPU developed at CEA-Leti using solid-state Qubits.
Design of in-memory high-dimensional-computing system
Conventional von Neumann architecture faces many challenges in dealing with data-intensive artificial intelligence tasks efficiently due to huge amounts of data movement between physically separated data computing and storage units. Novel computing-in-memory (CIM) architecture implements data processing and storage in the same place, and thus can be much more energy-efficient than state-of-the-art von Neumann architecture. Compared with their counterparts, resistive random-access memory (RRAM)-based CIM systems could consume much less power and area when processing the same amount of data. This makes RRAM very attractive for both in-memory and neuromorphic computing applications.
In the field of machine learning, convolutional neural networks (CNN) are now widely used for artificial intelligence applications due to their significant performance. Nevertheless, for many tasks, machine learning requires large amounts of data and may be computationally very expensive and time consuming to train, with important issues (overfitting, exploding gradient and class imbalance). Among alternative brain-inspired computing paradigm, high-dimensional computing (HDC), based on random distributed representation, offers a promising way for learning tasks. Unlike conventional computing, HDC computes with (pseudo)-random hypervectors of D-dimension. This implies significant advantages: a simple algorithm with a well-defined set of arithmetic operations, with fast and single-pass learning that can benefit from a memory-centric architecture (highly energy-efficient and fast thanks to a high degree of parallelism).
Simulation of silicon solar cells based on n-type material : modelling and architecture optimisation.
INES is actually developping new fabrication technologies for n-type silicon solar cells. Working on simulation of photovoltaic solar cells enables the speed-up of the developement of new technologies: physical interpretation of characterisation results, support to device design, optimisation of processing steps and evaluation of original designs.
This subject open for post-doc position is focused on the study of semi-empirical models for materials and process steps for n-type solar cells. These basic road-blocks will be assembled in a complete model by using a multi-scale simulation tool. In the end, this global model will allow optimising of the p-type emitter geometrical structure, the efficiency of carrier collection on the back side or the geometry of metallisation for electrical contacts.
modelling and Control of voltage and frequancy in GALS architecture submitted to Process-Voltage-Temperature variability
The evolution of sub-micron technologies has induced tremendous challenges the designer has to face, namely, the Process-Voltage-Temperature varibility and the decrase of power consumption for mobile applications.
The work to be done here concerns the DVFS (Dynamic Voltage and Frequency Scaling) policies for GALS (Globally Asynchronous, Locally Synchronous) architecture.
A fine grain modelling of the voltage and frequency “actuators” must be first done in order to simulate in a realistic ways the physical phenomena. Especially, the various parameters that may influence the system will be considered (process variation, supply voltage variation and noise, temperature variation, etc.)
Then, Non-Linear (NL) control laws that take into account the saturation of the actuators will be developed. These laws will be validated on the physical simulator and their performances in regulation (i.e. the response of the closed-loop system to disturbances such as PVT variations) will be evaluated. Note that these laws will be designed at the light of implementation constraints (mainly cost) in terms of complexity, area, etc.
Actually, the system considered here is intrinsically a Multi-Inputs-Multi-Outputs (MIMO) one. Therefore, its control can be design with NL techniques devoted to MIMO systems in order to ensure the requirements and reject the disturbances.
The control of several Voltage and Frequency Islands (VFI) is usually done via a “central brain” that chooses the voltage and frequency references thanks to a computational workload deadline. For more advanced architectures, the capabilities of each processing element, especially its maximum frequency, can be taken into account. A disruptive approach should be to consider a more distributed control that for instance takes into account the particular state (e.g. temperature) of each VFI neighbours. Control techniques that have been designed for distributed Network Controlled Systems could be adapted to MPSoCs.