Metamaterials : design of an integrated high-impedance surface at 60 GHz, transposition and potentialities at 60 THz
Invisibility cloaking, sub-wavelength, thin antenna substrates, absorbers, etc., metamaterial structures have open many perspectives, some of them seeming futuristic while other being very practical given the current ste of the art in the domains of materials, microtechnologies and integrated optics.
this post-doctoral work will focus on the study of high-impedance surfaces and the possibility of transposition of these designs between very different frequency bands (6 GHz, 60 GHz, 60 THz) corresponding to a wide range of technologies and applications.
After a thorough bibliographic study of the current state of the art, the developments will include the design of high-impedance surfaces at the three frequency bands cited above and an experimental demonstration at 6 GHz and possibly at 60 GHz.
Internet of Things applications: Ultra Low power and adaptive analog-to-digital converters in advanced FD-SOI process
The post-doctoral project aims to study Ultra Low Power and Adaptive Analog-to-Digital Converter (ADC) over a wide operating range of microsystem from Internet of Things or sensor networks applications.
The ADC is one of the main blocks into System on Chip (SoC) because of its position between physical signal treatment (Front-End) and digital treatment (Digital Base Band). Its performances in terms of resolution or frequency ranges affect the overall performances of the SoC. A particular consideration will be carrying out on power consumption and some reconfigurability technics will be used to adapt its consumption to the contextual performances required. To reduce as possible the ADC consumption, advanced FDSOI process will be used.
Based on Ultra Low Power constraints, the post-doctorate student will study the literature and will propose, design and experimentally demonstrate a relevant topology to increase the power efficiency and the performances of ADC by using advanced FDSOI process.
Electrical characterization of phase-change memories (PCM)
Main objectives of this postdoc position will be the electrical characterization in view of basic physical modelling of chalcogenide materials and integrated devices for application to sub-45nm embedded Phase-Change Non-Volatile Memories.
Electrical characterization (program dynamics, data-retention at different temperature, cycling, data-retention after cycling, disturb during cell reading and programming of nearby cells...) on test structures will be performed in order to put in evidence the main performances and degradation modes. Electrical characterization on blanket deposition will be operated as well, in order to assess the chalcogenide resistivity, crystallization temperature and thermal conductivity.
The postdoc will be involved in a detailed experimental work, but he will have also to face the theoretical principles governing the functionality of a Phase-Change Memory. In particular, the obtained experimental data will be coupled to a basic physical modeling of the chalcogenide materials integrated in the test structure, considering the electrical & thermal dynamics governing the phase change process of PCRAM devices.
Minimizing modifications at III-V pattern sidewalls after plasma etching for heterointegrated optoelectronics and nonlinear photonics
This project will focus on understanding plasma-induced damage at the sidewalls of micro-nano-patterned III-V semiconductors to find relevant technological solutions capable to minimize this damage. There is a clear need of knowledge on by which mechanisms and to what extent the plasma etching process modifies the III-V pattern sidewalls and the consequences it has on the device optical performances. The selected III-V semiconductor will be aluminium gallium arsenide which exhibits excellent optoelectronic properties and strong nonlinear parametric gain.
The student will be mainly focused on understanding how the key plasma process parameters influence the structural and chemical changes at the III-V sidewalls, as well as changes of optical properties. This will require the development of a methodology for a 3D quantitative characterization of the sidewalls at the nanoscale, based on Auger microscopy and cathololuminescence. The main objective will be to correlate plasma-induced structural defects and modifications of the optoelectronics properties. The second step will consist in developing optimized plasma etching processes for III-V semiconductors, exploring alternative plasma technologies. You will also be involved in the development of processes for restoring and passivating the AlGaAs sidewalls.
Electro-optical characterisation for Vis-IR active devices
With the Integration of Heterogeneous Components Department, the Lab of Technologies and Components for Visualisation (DIHS/LTCV) develops OLED devices. One of its main topics is aimed at producing hybrid OLEDs, hybrid standing for the mix of deposition techniques : wet and evaporation. Target applications come from micro displays to photodetectors via lighting.
For the development of hybrid OLEDs, DIHS/LTCV lab is looking for a Post_doc specialised in Organic Electronic to work in a fundamental research project. You will be in charge of stack development and of the characterisation method development for OLEDs devices.The optimisation of the cavity will be done based on the physical parameters of the different layers.
At the same time, IV, CV and photoluminescence analyses will be adapted in visible and IR range.
Finally, the layers interface study by impedance spectroscopy and Hall effect will be done.
Error Coding Driven Synthesis of Combinational Circuits from Unreliable Components
With the advent of nanoelectronics, the reliability of the forthcoming circuits and computation devices is becoming questionable. Indeed, due to huge increases in density integration, lower supply voltages, and variations in the technological process, MOS and emerging nanoelectronic devices will be inherently unreliable. As a consequence, the nanoscale integration of chips built out of unreliable components has emerged as one of the most critical challenges for the next-generation electronic circuit design. To make such nanoscale integration economically viable, new solutions for efficient and fault-tolerant data processing and storage must now be invented.
This post-doctoral position aims at investigating innovative fault-tolerant solutions, at both device- and system-level, that are fundamentally rooted in mathematical models, algorithms, and techniques of information and coding theory. Investigated solutions will build on specific error correcting codes, able to provide reliable error protection even if they themselves operate on unreliable hardware. The goal is to develop the scientific foundation and provide a first proof-of-concept, as an essential condition for bringing about a paradigm shift in the design of future nanoscale circuits.
Development and characterization of concentrator photovoltaic (CPV) receivers for high-efficiency CPV modules
Concentrator photovoltaics (CPV) arises as a promising technology capable of economically justify the use of highly efficient (and highly expensive) monolithically stacked multijunction solar cells (MJSC). CPV takes advantage of low-cost optical elements, such as mirrors or lenses, to capture the sunlight and concentrate it into small-size cells, exchanging solar cell surface by optical elements. This technology, which is at an industrial stage, uses state-of-the-art triple junction (3J) solar cells with efficiencies up to 45%.
The postdoc position here proposed will deal with novel architectures of CPV receivers conceived from high-efficiency MJSC that will be integrated in next-generation CPV modules. The research engineer will also need to learn how to characterize these systems, for which he/she will use the tools available at the CPV Lab at INES (CEA). Novel characterization techniques may also be required.
The candidate must have a M.S. in Physics or Engineer with specialization on solid state physics, electronics, electrical engineering, mechatronics or similar. He/she must be a PhD, preferably in the field of photovoltaics and particularly on CPV. Good language skills and laboratory experience are required.
Intégration CMOS à canal dual en technologie FDSOI : comparaison "enrichissement en Ge" vs. "Epitaxie localisée"
LETI is a major laboratory in the european microelectronics research, especially in the thin film FDSOI research (Fully Depleted). We propose innovative solutions for the next ITRS roadmap generations (sub 22nm), such as the integration of ultrathin Silicon-Germanium (SiGe) layers in the channel of p type transistors (in order to increase the hole mobility, and to adjust the threshold voltage of pMOSFETs).
The first results show significative gains for hole mobilityy and Vth,p tunning (C. Le Royer et al. ESSDERC 2010, IEDM 2011) but also for basic circuits (L. Hutin et al. IEDM 2010).
In order to further improve the Fully Depleted CMOS DualChannel integration, it is necessary to quantify in details the advantages and the possible drawbacks (form the process and from the electrical performance point of view). LETI wants to compare the two following approaches for SiGe based pMOSFETs (cointegrated with SOI nMOSFETs featuring 6nm body thickness):
.SiGe/SOI hetrostructures ("Localized SiGe epi" on SOI)
.SiGe-On-Insulator ("localized Ge enrichment" on SOI)
Other issues have also to be considered such as the initial substrate (SOI, sSOI) or the Ge content in the SiGe layer…
Low temperature process modules for 3d coolcube integration : through the end of roadmap
3D sequential integration is envisaged as a possible solution until the end of CMOS roadmap. Different process modules have been developped @ 500°C for planar FDSOI technology in a gate first process. However, regarding bottom transistor level stability in CoolcubeTM integration, and yield consideration, the need to reduce further the top transistor temperature down to 450°C should be explored.
The post-doc will have in charge the development of specific technological modules at low temperature both 500°C and 450°C for FDSOI planar devices to acquire a solid knowledge in low temperature CMOS process integration. The specific low temperature gate module will be addressed on planar devices. The threshold voltage modulation will also be studied.
The work will be performed in collaboration with the technological platform process of LETI for the low temperature modules development. The electrical characterization in collaboration with the characterization laboratory and the TCAD simulations team of LETI.