DTCO for RF & mmW Applications:Focus on Homogeneous & Heterogeneous Chiplet Hybrid Bonding Challenge
In recent years, there have been numerous technological advancements in silicon-based semiconductors. However, the limits in terms of frequency performance and power seem to have been reached, requiring the development of new type III-V devices (such as InP and GaN) that are faster, more powerful and well adapted for new RF mmW applications. For reasons of flexibility, performance, and cost, it is crucial to co-integrate these new high-performance III-V components with the more traditional silicon technologies. This is one of the major objectives of the proposed topic.
The focus will be on the design and optimisation of millimetre-wave RF circuits using 3D heterogeneous hybrid bonding assembly technology. In recent years, numerous test vehicles have been fabricated and characterised to demonstrate the advantages and disadvantages of the hybrid bonding assembly process for millimetre wave RF applications. The aim is to extend this work and focus the studies and research on real RF systems, such as millimetre-wave power amplifiers. The DTCO (Design and Technology Co-Optimisations) approach will not only enable the design of efficient 3D RF circuits, but will also allow the adaptation of different 3D design rules to make 3D hybrid bonding technology relevant for the production of millimetre-scale 3D integrated systems.
2D materials electrical characterization for microelectronics
Future microelectronic components will be ever smaller and ever more energy-efficient. To meet this challenge, 2D materials are excellent candidates, thanks to their remarkable dimensions and electronic properties (high mobility of charge carriers, high light emission/absorption). What's more, they feature van der Waals (vdW) surfaces, i.e. no dangling bonds, enabling them to retain their properties even at very small dimensions (down to the monolayer). New 2D materials and vdW stacks with novel physical properties are being discovered every day. However, integrating them and measuring their performance in circuits remains an ongoing challenge, as their properties must be preserved during integration.
The aim of this post-doc is to develop components for qualifying 2D materials for microelectronic (RF transistor) and spintronic (magnetic memory) applications in horizontal configuration on silicon. A vertical measurement method has already been developed by CEA LETI. Building on these developments, the candidate will develop this measurement system and characterize various materials produced in MBE by CEA-IRIG. The work will involve transferring these layers onto chips, optimizing the electrical contacts and developing the in-plane electrical measurement chain.
Comparison of Diamond and vertical GaN technologies to SiC and Si for power applications
Power devices based on wide band gap semiconductors are increasingly being studied and adopted in commercial products, driven by the electrification of our societies. Among these wide band gap devices, SiC-based technologies are the most mature, at the industrial production stage. Other materials are being studied to achieve higher performance, in particular diamond, whose intrinsic physical properties offer great potential, as well as GaN components in a vertical architecture. However, the real benefits of these materials compared with existing Si or SiC solutions have not been clearly demonstrated and might strongly depend on the applications considered. The aim of this project is to identify one or more applications where vertical GaN and diamond technologies are likely to bring significant benefits, taking into account the current and/or projected market for these applications. Then, using TCAD and SPICE simulations as well as experimental test device characterizations, we will compare the estimated performance of industrially viable diamond and GaN components, designed for these applications, with that of SiC and Si.
Disruptive RF substrates based on polycrystalline materials
A high resistivity substrate is essential for the design of state-of-the-art high-frequency circuits. The high-resistivity (HR) SOI substrate with a trap-rich layer below the buried oxide (BOX) is the option with the highest performance at present for CMOS technologies. However, these substrates have two major limitations: (1) their relatively high price and (2) the degradation of their RF performance at operating temperatures above 100 °C.
As part of this postdoctoral study, we propose to study, in collaboration with the Catholic University of Louvain (UCL), the RF performance over a wide temperature range of a polycrystalline substrate over its entire thickness (several hundred µm). These polycrystalline substrates indeed have a high density of electronic traps distributed throughout the entire volume, which in principle allows for stable RF performance even at high operating temperatures.
The person hired will participate in the following research: (1) screening of promising substrates from TCAD simulations (e.g. poly-Si, poly-SiC, …), (2) integration of polycrystalline substrates in an SOI process flow at Leti, (3) measurement of RF performances in frequency and temperature at UCL. A particular attention will be placed on understanding the physical phenomena involved through the comparison of experimental and simulation data.
Strain driven Group IV photonic devices: applications to light emission and detection
Straining the crystal lattice of a semiconductor is a very powerful tool enabling controlling many properties such as its emission wavelength, its mobility…Modulating and controlling the strain in a reversible fashion and in the multi% range is a forefront challenge. Strain amplification is a rather recent technique allowing accumulating very significant amounts of strain in a micronic constriction, such as a microbridge (up to 4.9% for Ge [1]), which deeply drives the electronic properties of the starting semiconductor. Nevertheless, the architectures of GeSn microlasers under strong deformation and recently demonstrated in the IRIG institute [2] cannot afford modulating on demand the applied strain and thus the emission wavelength within the very same device, the latter being frozen “by design”. The target of this 18 months post doc is to fabricate photonic devices of the MOEMS family (Micro-opto-electromechanical systems) combining the local strain amplification in the semiconductor and actuation features via an external stimulus, with the objectives to go towards: 1-a wide band wavelength tunable laser microsource and 2-new types of photodetectors, both in a Group IV technology (Si, Ge and Ge1-xSnx). The candidate will conduct several tasks at the crossroads between fabrication and optoelectronic characterization:
a-simulation of the mechanical operation of the expected devices using FEM softwares, and calculation of the electronic states of the strained semiconductor
b-fabrication of devices at the Plateforme Technologique Amont (lithography, dry etching, metallization, bonding), based on results of a
c-optical and material characterization of the fabricated devices (PL, photocurrent, microRaman, SEM…) at IRIG-PHELIQS and LETI.
A PhD in the field of semiconductors physics or photonics, as well as skills in microfabrication are required.
[1] A. Gassenq et al, Appl. Phys. Lett.108, 241902 (2016)
[2] J. Chrétien et al, ACS Photonics2019, 6, 10, 2462–2469
Development of irradiation resistant silicon materials and integration in photovoltaïcs cells for space applications
Historically, photovoltaic (PV) energy was developed together with the rise of space exploration. In the 90’s, multijunction solar cells based on III-V materials progressively replaced silicon (Si) cells, taking advantage of higher efficiency levels and electrons/protons irradiation resistance. Nowadays, the space environment is again looking at Si based PV applications: request of higher PV power, moderated space mission lengths, cost reduction issues (€/W Si ~ III-V/500), higher efficiencies p-type Si PV cells… Solar cells are exposed to cosmic irradiation in space, especially to electrons and protons fluxes. The latter’s affect the cells performances, essentially because of bulk defect formations and charge carrier recombination. In order to use Si based solar cells in space, we need to increase their irradiation resistance, which is the main goal of this post-doc position. To do so, the work will first consist in elaborating new Si materials, with increased irradiation resistance. Compositional aspects of the Si will be modified, particularly by introducing elements limiting the formation of bulk defects under irradiations, developing electrical passivation properties. The electronic properties of the materials will be deeply characterized before and after controlled irradiation. Then, this Si material will be used to fabricate heterojunction solar cells. Their performances will be evaluated again before and after irradiation. Such experimental work could be supported by numerical simulation at the device scale.
Development of large area substrates for power electronics
Improving the performance of power electronics components is a major challenge for reducing our energy consumption. Diamond appears as the ultimate candidate for power electronics. However, the small dimensions and the price of the substrates are obstacles to the use of this material. The main objective of the work is to overcome these two difficulties by slicing the samples into thin layers by SmartCut™ and by tiling these thin layers to obtain substrates compatible with microelectronics.
For this, various experiments will be carried out in a clean room. Firstly, the SmartCut™ process must be made more reliable. Characterizations such as optical microscopy, AFM, SEM, Raman, XPS, electrical, etc. will be carried out in order to better understand the mechanisms involved in this process.
The candidate might be required to work on other wide-gap materials studied in the laboratory such as GaN and SiC, which will allow him to have a broader view of substrates for power electronics.
Design of 2D Matrix For Silicum Quantum computing with Validation by Simulation
The objective is to design a 2D matrix structure for quantum computing on silicon in order to consider structures of several hundred physical Qubits.
In particular the subject will be focused on:
- The functionality of the structure (Coulomb interaction, RF and quantum)
- Manufacturing constraints (simulation and realistic process constraint)
- The variability of the components (Taking into account the variability parameter and realistic defectivity)
- The constraints induced on the algorithms (error correction code)
- Scalability of the structure to thousands of physical Qubits
The candidate will work within a project of more than fifty people with expertise covering the design, fabrication, characterization and modeling of spin qubits as well as related disciplines (cryoelectronics, quantum algorithms, quantum error correction, …)
Developement of relaxed pseudo-substrate based on InGaN porosified by electrochemical anodisation
As part of the Carnot PIRLE project starting in early 2021, we are looking for a candidate for a post-doctoral position of 24 months (12 months renewable) with a specialty in material science. The project consists in developing a relaxed pseudo-substrate based on III-N materials for µLEDs applications, especially for emission in red wavelength. The work will focus on developing an InGaN-based epitaxy MOCVD growth process, on an innovative substrate based on electrochemically anodized and relaxed materials. He (She) will have characterize both the level of relaxation of the re-epitaxied layer and its crystalline quality. These two points will promote the epitaxial regrowth of an effective red LED. The candidate will be part of the team, working on the PIRLE project, will be associated to the work on red LED growth and its optical and electro-optical characterizations.
Development of innovative metal contacts for 2D-material field-effect-transistors
Further scaling of Si-based devices below 10nm gate length is becoming challenging due to the control of thin channel thickness. For gate length smaller than 10nm, sub-5nm thick Si channel is required. However, the process-induced Si consumption and the reduction of carrier mobility in ultrathin Si layer can limit the channel thickness scaling. Today, the main contenders that allow the extension of the roadmap to ultra-scaled devices are 2D materials, particularly the semiconducting transition metal dichalcogenides (TMD). Due to their unique atomically layered structure, they offer improved immunity to short-channel-effects in comparison to usual Si-based field-effect-transistors (FETs). This makes them very attractive for the application of more-Moore electronics.
However, the scalability of MOSFET device and the introduction of new material make source and drain contact a major issue. If many efforts have been made, in the past years, to reduce Fermi level pinning and Schottky barrier height, for many, these approaches are not industrially scalable. The main objective of this work is then to propose an in-depth understanding of electrical contact characteristics (based on different material) to identify the lowest contact resistance. The processes involved, offering an optimal contact resistance, must be compatible with wafer-scale processing for an integration in our 200/300mm advanced CMOS platform. The post-doc will in-depth study mechanisms enabling the formation of small contact resistances (between MoS2 and metal). It will have to identify the most promising contact material and to develop the associated deposition processes (ALD/PVD). Finally, electrical characterization of contact will be performed to qualify both material and interfaces enabling optimal operation of future 2D FETs