Advances in materials, transistor architectures, and lithography technologies have enabled exponential growth in the performance and energy efficiency of integrated circuits. New research directions, including operation at cryogenic temperatures, could lead to further progress. Cryogenic electronics, essential for manipulating qubits at very low temperatures, is rapidly developing. Processors operating at 4.2 K using 1.4 zJ per operation have been proposed, based on superconducting electronics. Another approach involves creating very fast sequential processors using specific technologies and low temperatures, reducing energy dissipation but requiring cooling. At low temperatures, the performance of advanced CMOS transistors increases, allowing operation at lower voltages and higher operating frequencies. This could improve the sequential efficiency of computers and simplify the parallelization of software code. However, materials and component architectures need to be rethought to maximize the benefits of low temperatures. The post-doctoral project aims to determine whether cryogenic temperatures offer sufficient performance gains for CMOS or should be viewed as a catalyst for new high-performance computing technologies. The goal is particularly to assess the increase in processing speed with conventional silicon components at low temperatures, integrating measurements and simulations.

In the near future, emerging quantum information technologies are expected to lead to global breakthroughs in high performance computing and secure communication. Among semiconductor approaches, silicon-based spin quantum bits (qubits) are promising thanks to their compactness featuring long coherence time, high fidelity and fast qubit rotation [Maurand2016], [Meunier2019]. A main challenge is now to achieve individual qubit control inside qubit arrays.

Qubit array constitutes a compact open system, where each qubit cannot be considered as isolated since it depends on the neighboring qubit placement, their interconnection network and the back-end-line stack. The main goal of this post-doctoral position is to develop various implementation of spin control on 2D qubit array using multi-scale electromagnetic (EM) simulation ranging from nanometric single qubit up to millimetric interconnect network.

The candidate will i) characterize radio-frequency (RF) test structures at cryogenic temperature using state-of-the-art equipment and compare results with dedicated EM simulations, ii) evaluate the efficiency of spin control and allow multi-scale optimization from single to qubit arrays [Niquet2020], iii) integrate RF spin microwave control for 2D qubit array using CEA-LETI silicon technologies.

The candidate need to have a good RF and microelectronic background and experience in EM simulation, and/or design of RF test structures and RF characterization. This work takes place in a dynamic tripartite collaborative project between CEA-LETI, CEA-IRIG and CNRS-Institut Néel (ERC “Qucube”).

For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items. Things will change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. At LETI, we will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory.
The post-doc will perform electrical characterizations of CMOS transistors and Resistive RAMs in order to calibrate models and run TCAD/spice simulations to drive the technology developments and enable the circuit designs.