Modeling of charge noise in spin qubits

Thanks to strong partnerships between several research institutes, Grenoble is a pioneer in the development of future technologies based on spin qubits using manufacturing processes identical to those used in the silicon microelectronics industry. The spin of a qubit is often manipulated with alternating electrical (AC) signals through various spin-orbit coupling (SOC) mechanisms that couple it to electric fields. This also makes it sensitive to fluctuations in the qubit's electrical environment, which can lead to large qubit-to-qubit variability and charge noise. The charge noise in the spin qubit devices potentially comes from charging/discharging events within amorphous and defective materials (SiO2, Si3N4, etc.) and device interfaces. The objective of this postdoc is to improve the understanding of charge noise in spin qubit devices through simulations at different scales. This research work will be carried out using an ab initio type method and also through the use of the TB_Sim code, developed within the CEA-IRIG institute. This last one is able of describing very realistic qubit structures using strong atomic and multi-band k.p binding models.

Design of Ising Machines based on a network of spintronics oscillators copled through CMOS circuitry

Our information and communication society is asking for always more computing tasks of increasing complexity. Their energy bargain increases quickly so that it is mandatory to find new architecture of computing processors with improved energy efficiency.
The post doc applicant will contribute to the design of Ising machines which are computing architectures inspired from biology and physics and which permit to solve complex optimization problems. Under the scope of SpinIM project (french ANR funding), the applicant will contribute to the demonstration of an Ising machine based on the electrical coupling of spin torque nano-oscillators (STNO). More specifically, the post doc role will be to design the configurable CMOS chip implementing the electrical coupling. He will have to propose a VerilogA model of the STNO with the help of Spintec experience on STNO theory. Then the post doc will have to propose an optimized design of the CMOS chip from schematics to layout and he will have to assess the chip performances in laboratory. Finally, the post doc will participate to the demonstration of the full Ising machine consisting of the CMOS chip and a STNO network on some optimization tasks. The post doc will take place in the LGECA laboratory of CEA-Leti which have gained experience on CMOS-Spintronics co-design.

Design and fabrication of the magnetic control of 1.000 qubits arrays

Quantum computing is nowadays a strong field of research at CEA-LETI and in numerous institutes and companies around the world. In particular, RF magnetic fields allow to control the spin of silicon qubits, and pathway for large scale control is a real technological challenge.
The bibliographic analysis and the studies already carried out will able to draw out the pros and cons of the various existing solutions. In collaboration with integration, simulation and design staff, a proof of concept will be develloped and fabricated.

Multi-scale modeling of the electromagnetic quantum dot environment

In the near future, emerging quantum information technologies are expected to lead to global breakthroughs in high performance computing and secure communication. Among semiconductor approaches, silicon-based spin quantum bits (qubits) are promising thanks to their compactness featuring long coherence time, high fidelity and fast qubit rotation [Maurand2016], [Meunier2019]. A main challenge is now to achieve individual qubit control inside qubit arrays.

Qubit array constitutes a compact open system, where each qubit cannot be considered as isolated since it depends on the neighboring qubit placement, their interconnection network and the back-end-line stack. The main goal of this post-doctoral position is to develop various implementation of spin control on 2D qubit array using multi-scale electromagnetic (EM) simulation ranging from nanometric single qubit up to millimetric interconnect network.

The candidate will i) characterize radio-frequency (RF) test structures at cryogenic temperature using state-of-the-art equipment and compare results with dedicated EM simulations, ii) evaluate the efficiency of spin control and allow multi-scale optimization from single to qubit arrays [Niquet2020], iii) integrate RF spin microwave control for 2D qubit array using CEA-LETI silicon technologies.

The candidate need to have a good RF and microelectronic background and experience in EM simulation, and/or design of RF test structures and RF characterization. This work takes place in a dynamic tripartite collaborative project between CEA-LETI, CEA-IRIG and CNRS-Institut Néel (ERC “Qucube”).

Digital circuit design for In-Memory Computing in advanced Resistive-RAM NVM technology

For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
CEA-Leti launched a project on this topic, leveraging three key enabling technologies, under development at CEA-Leti: non-volatile resistive memory (RRAM), new energy-efficient nanowire transistors and 3D-monolithic integration [ArXiv 2012.00061]. A 3D In-Memory-Computing accelerator circuit will be designed, manufactured and measured, targeting a 20x reduction in (Energy x Delay) Product vs. Von-Neumann systems.

Simulation and electrical characterization of an innovative logic/memory CUBE for In-Memory-Computing

For integrated circuits to be able to leverage the future “data deluge” coming from the cloud and cyber-physical systems, the historical scaling of Complementary-Metal-Oxide-Semiconductor (CMOS) devices is no longer the corner stone. At system-level, computing performance is now strongly power-limited and the main part of this power budget is consumed by data transfers between logic and memory circuit blocks in widespread Von-Neumann design architectures. An emerging computing paradigm solution overcoming this “memory wall” consists in processing the information in-situ, owing to In-Memory-Computing (IMC).
However, today’s existing memory technologies are ineffective to In-Memory compute billions of data items. Things will change with the emergence of three key enabling technologies, under development at CEA-LETI: non-volatile resistive memory, new energy-efficient nanowire transistors and 3D-monolithic integration. At LETI, we will leverage the aforementioned emerging technologies towards a functionality-enhanced system with a tight entangling of logic and memory.
The post-doc will perform electrical characterizations of CMOS transistors and Resistive RAMs in order to calibrate models and run TCAD/spice simulations to drive the technology developments and enable the circuit designs.

Nanofabrication of spintronic spiking neurons

In the frame of the French national ANR project SpinSpike, Spintec laboratory is opening a postdoctoral researcher position. The candidate will work in collaboration with UMPhy CNRS-Thales and Thales TRT. The objective is the realization of proof-of-concept magnetic tunnel junction based artificial spiking neurons able to generate spikes and propagate them between coupled artificial neurons.
The candidate should have a strong background in nanofabrication and should be familiar with common techniques of optical and e-beam lithography as well as different etching techniques. The candidate can also be involved in the electrical characterization of the devices.
The position is expected to start on April 1, 2021 and go on for up to 2 years jointly between the RF team and MRAM teams of Spintec. The contract will be managed by CEA and funded by ANR Agency.
We offer an international and competitive environment, state-of-the-art equipment, and the possibility to perform research at the highest level. We promote teamwork in a diverse and inclusive environment and welcome all kinds of applicants. Further information about Spintec laboratory www.spintec.fr .

Scalable digital architecture for Qubits control in Quantum computer

Scaling Quantum Processing Units (QPU) to hundreds of Qubits leads to profound changes in the Qubits matrix control: this control will be split between its cryogenic part and its room temperature counterpart outside the cryostat. Multiple constraints coming from the cryostat (thermal or mechanical constraints for example) or coming from Qubits properties (number of Qubits, topology, fidelity, etc…) can affect architectural choices. Examples of these choices include Qubits control (digital/analog), instruction set, measurement storage, operation parallelism or communication between the different accelerator parts for example. This postdoctoral research will focused on defining a mid- (100 to 1,000 Qubits) and long-term (more than 10,000 Qubits) architecture of Qubits control at room temperature by starting from existing QPU middlewares (IBM QISKIT for example) and by taking into account specific constraints of the QPU developed at CEA-Leti using solid-state Qubits.

DTCO analysis of MRAM for In/Near-Memory Computing

The energy cost associated to moving data across the memory hierarchy has become a limiting factor in modern computing systems. To mitigate this trend, novel computing architectures favoring a more local and parallel processing of the stored information are proposed, under the labels « Near/In-Memory Computing » or « Processing In Memory ». Substantial benefits are expected in particular for computationally complex (e.g. combinatorial optimization, graph analysis, cryptography) and data-intensive tasks (e.g. video stream analysis, bio-informatics). Such applications are especially demanding in terms of endurance, latency and density. SRAM, fulfilling the first two criteria, may eventually suffer from its footprint and static power consumption. This prompts the evaluation of alternative denser and non-volatile memory technologies, with magnetoresistive memories (MRAM) currently leading in terms of speed-endurance trade-off.

The primary objective will be to estimate improvements brought by MRAM in terms of array-level power, performance, area (PPA), as compared to SRAM-based on-chip memories and for advanced technology nodes. The candidate will establish an analysis and benchmarking workflow for various classes of MRAM, and optimize single bit cells based on a compact model for the memory element. This baseline approach will then be adapted to functional variations specific to IMC in order to assess the benefits of MRAM on an integrated test vehicle.

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