Private Set Intersection (PSI) is a cryptographic protocol that allows two (or more) parties, each holding a set of items, to compute the intersection of their sets without revealing any items outside the intersection. That is, each party learns only which items they have in common, and nothing else about the other’s data. For example, two companies could collaborate to find out which customers they share without disclosing any customers that are unique to one company. PSI is a special case of secure multi-party computation focusing on set overlap; it has applications in private contact discovery, privacy-preserving data mining,..In this thesis, we study PSI improvements with fully holomorphic encryption.

Critical systems have both functional and timing requirements, the latter ensuring that deadlines are always met during operation; failure to do so may lead to catastrophic consequences. The critical nature of such systems demands specialized hardware and software solutions. This PhD thesis topic focuses on the development of computer architecture designs for critical systems, known as predictable architectures, capable of providing the necessary timing guarantees. Several such architectures exist, typically based on in-order pipelines and incorporating behavioral restrictions (e.g., disabling complex speculation mechanisms) or structural specializations (e.g., redesigned caches or deterministic arbitration for shared resources). These restrictions and specializations inevitably impact performance, and the design of predictable architectures must therefore address the predictability–performance tradeoff directly. This PhD thesis aims to explore this tradeoff in a novel way, by adapting a high-performance variant of an in-order processor (CVA6) and developing top-down techniques to make it predictable. Performance in such processors is usually achieved through mechanisms like branch prediction, prefetching, and value prediction, implemented via specialized storage elements (e.g., buffers) and supported by control mechanisms such as rollback on misprediction. Within this context, the goal of the thesis is to define a general predictability scheme for speculative execution, covering both storage organization and rollback behavior.

Fully Homomorphic Encryption (FHE) is a technology that allows computations to be performed directly on encrypted data, meaning that we can process information without ever knowing its actual content. For example, it could enable online searches where the server never sees what you are looking for, or AI inference tasks on private data that remain fully confidential. Despite its potential, current FHE implementations remain computationally intensive and require substantial processing power, typically relying on high-end CPUs or GPUs with significant energy consumption. In particular, the bootstrapping operation represents a major performance bottleneck that prevents large-scale adoption. Existing CPU-based FHE implementations can take over 20 seconds on standard x86 architectures, while custom ASIC solutions, although faster, are prohibitively expensive, often exceeding 150 mm² in silicon area. This PhD project aims to accelerate the TFHE scheme, a more lightweight and efficient variant of FHE. The objective is to design and prototype innovative implementations of TFHE on RISC-V–based systems, targeting a significant reduction in bootstrapping latency. The research will explore synergies between hardware acceleration techniques developed for post-quantum cryptography and those applicable to TFHE, as well as tightly coupled acceleration approaches between RISC-V cores and dedicated accelerators. Finally, the project will investigate the potential for integrating a fully homomorphic computation domain directly within the processor’s instruction set architecture (ISA).

Modern distributed architectures are becoming increasingly heterogeneous and dynamic, expanding the attack surface and challenging traditional, static security mechanisms. To address these challenges, proactive defense approaches, and particularly Moving Target Defense (MTD), have been introduced to disrupt attackers by regularly modifying the system configuration — for instance, by randomizing network addresses, reallocating containers, or deploying decoy services. However, most existing strategies remain static, rely on a single defense mechanism, and ignore the underlying hardware state. In parallel, hardware-level countermeasures such as cache partitioning, randomization, and scheduling have been proposed against side-channel attacks, yet they are seldom integrated into the decision logic of orchestration frameworks.

The objective of this PhD is to design an adaptive MTD orchestration framework that is aware of the underlying hardware state, capable of dynamically adjusting defense strategies according to system load, performance, and observed vulnerability. The central idea is to feed a reinforcement learning (RL) agent with information derived from hardware performance counters and local security metrics linked to shared cache dynamics, enabling it to select the optimal combination of MTD strategies based on the current system context.

The expected contributions include the definition of a hardware-informed local security metric capturing cache behavior, the graph-based modeling of dependencies between services, resources, and attack surfaces, the design of a unified RL-based decision agent for adaptive MTD selection, and a multi-criteria evaluation (security, performance, energy) on a realistic automotive use case.

This thesis aims to bridge system-level and hardware-level perspectives to build trustworthy orchestrators capable of anticipating and adapting defenses against evolving threats, paving the way toward intelligent and hardware-aware proactive security in distributed systems.