Laser Fault Injection Applied to Reverse Engineering of Memories
Memories play a critical role for the security of cyber-physical systems. They manage sensitive data such as cryptographic keys and proprietary codes. With the increasing threat of hardware attacks, understanding and manipulating memory organization has become essential. The thesis aims to explore the application of laser attack techniques, specifically Thermal Laser Stimulation (TLS) and laser perturbation, to reverse engineer memory systems. The primary objective is to develop methods for extracting or modifying memory content, with a particular focus on validating TLS on FDSOI 22nm technology. Additionally, the thesis seeks to use laser perturbation for reconstructing memory architecture, analyzing error-correcting codes, and designing countermeasures. The research will leverage the infrastructures available at CEA (e.g.,https://github.com/CEA-Leti/secbench), as well as the expertise of the laboratory members.
Defense of scene analysis models against adversarial attacks
In many applications, scene analysis modules such as object detection and recognition, or pose recognition, are required. Deep neural networks are nowadays among the most efficient models to perform a large number of vision tasks, sometimes simultaneously in case of multitask learning. However, it has been shown that they are vulnerable to adversarial attacks: Indeed, it is possible to add to the input data some perturbations imperceptible by the human eye which undermine the results during the inference made by the neural network. However, a guarantee of reliable results is essential for applications such as autonomous vehicles or person search for video surveillance, where security is critical. Different types of adversarial attacks and defenses have been proposed, most often for the classification problem (of images, in particular). Some works have addressed the attack of embedding optimized by metric learning, especially used for open-set tasks such as object re-identification, facial recognition or image retrieval by content. The types of attacks have multiplied: some universal, other optimized on a particular instance. The proposed defenses must deal with new threats without sacrificing too much of the initial performance of the model. Protecting input data from adversarial attacks is essential for decision systems where security vulnerabilities are critical. One way to protect this data is to develop defenses against these attacks. Therefore, the objective will be to study and propose different attacks and defenses applicable to scene analysis modules, especially those for object detection and object instance search in images.
Secure and Agile Hardware/Software Implementation of new Post-Quantum Cryptography Digital Signature Algorithms
Cryptography plays a fundamental role in securing modern communication systems by ensuring confidentiality, integrity, and authenticity. Public-key cryptography, in particular, has become indispensable for secure data exchange and authentication processes. However, the advent of quantum computing poses an existential threat to many of the traditional public-key cryptographic algorithms, such as RSA, DSA, and ECC, which rely on problems like integer factorization and discrete logarithms that quantum computers can solve efficiently. Recognizing this imminent challenge, the National Institute of Standards and Technology (NIST) initiated in 2016 a global effort to develop and standardize Post-Quantum Cryptography (PQC). After three rigorous rounds of evaluation, NIST announced its first set of standardized algorithms in 2022. While these algorithms represent significant progress, NIST has expressed an explicit need for additional digital signature schemes that leverage alternative security assumptions, emphasizing the importance of schemes that offer shorter signatures and faster verification times to enhance practical applicability in resource-constrained environments. Building on this foundation, NIST opened a new competition to identify additional general-purpose signature schemes. The second-round candidates, announced in October 2024, reflect a diverse array of cryptographic families.
This research focuses on the critical intersection of post-quantum digital signature algorithms and hardware implementations. As the cryptographic community moves toward adoption, the challenge lies not only in selecting robust algorithms but also in deploying them efficiently in real-world systems. Hardware implementations, in particular, must address stringent requirements for performance, power consumption, and security, while also providing the flexibility to adapt to multiple algorithms—both those standardized and those still under evaluation. Such agility is essential to future-proof systems against the uncertainty inherent in cryptographic transitions. The primary objective of this PhD research is to design and develop hardware-agile implementations for post-quantum digital signature algorithms. The focus will be on supporting multiple algorithms within a unified hardware framework, enabling seamless adaptability to the diverse needs of evolving cryptographic standards. This involves an in-depth study of the leading candidates from NIST’s fourth-round competition, as well as those already standardized, to understand their unique computational requirements and security properties. Special attention will be given to designing modular architectures that can support different signatures, ensuring versatility and extensibility. The proposed research will also explore optimizations for resource efficiency, balancing trade-offs between performance, power consumption, and area utilization. Additionally, resilience against physical attacks (side-channel attacks and fault injection attacks) will be a key consideration in the design process. This PhD project will be conducted within the PEPR PQ-TLS project in collaboration with the TIMA laboratory (Grenoble), the Agence nationale de la sécurité des systèmes d’information (ANSSI) and INRIA.
HW/SW Contracts for Security Analysis Against Fault Injection Attacks on Open-source Processors
This thesis focuses on the cybersecurity of embedded systems, particularly the vulnerability of processors and programs to fault injection attacks. These attacks disrupt the normal functioning of systems, allowing attackers to exploit weaknesses to access sensitive information. Although formal methods have been developed to analyze the robustness of systems, they often limit their analyses to hardware or software separately, overlooking the interaction between the two.
The proposed work aims to formalize hardware/software (HW/SW) contracts specifically for security analysis against fault injection. Building on a hardware partitioning approach, this research seeks to mitigate scalability issues related to the complexity of microarchitecture models. Expected outcomes include the development of techniques and tools for effective security verification of embedded systems, as well as the creation of contracts that facilitate the assessment of compliance for both hardware and software implementations. This approach could also reduce the time-to-market for secure systems.
New machine learning methods applied to side-channel attacks
Products secured by embedded cryptographic mechanisms may be vulnerable to side-channel attacks. Such attacks are based on the observation of some physique quantities measured during the device activity, whose variation may provoke information leakage and lead to a security flaw.
Today, such attacks are improved, even in presence of specific countermeasures, by deep learning based methods.
The goal of this thesis is go get familiarity with semi-supervised and self-supervised Learning state-of-the-art and adapt promising methods to the context of the side-channel attacks, in order to improve performances of the attacks in very complex scenarios. A particular attention will be given to attacks against secure implementations of post-quantum cryptographic algorithms.
Cryptographic security of RISC-V processor enclaves with CHERI
CHERI (Capability Hardware Enhanced RISC Instructions) is a solution for securing the processor against spatial and temporal memory leaks by transforming any pointer into a capability that clearly defines the access limits to the data or instructions addressed.
In this thesis, we propose to enrich CHERI and its control-flow integrity capabilities on a RISC-V application processor, by protecting instructions right up to their execution against any type of modification. Secondly, based on authenticated memory encryption, we will study the possibility of using CHERI to define secure enclaves enabling cryptographic isolation between processes. The processor will be modified so that each process is encrypted with its own key and can have a secure life cycle. All keys must be efficiently protected in hardware.
Contact : olivier.savry@cea.fr
Combining over and underapproximation of memory abstractions for low-level code analysis
Rice's theorem stating that no method can automatically tell whether a property of a program is true or not has led to the separation of verification tools into two groups: sound tools operating by over-approximation, such as abstract interpretation, are able to automatically prove that certain properties are true, but are sometimes unable to conclude and produce alarms; conversely, complete tools operating by under-approximation, such as symbolic execution, are able to produce counter-examples, but are unable to demonstrate whether a property is true.
*The general aim of the thesis is to study the combination of sound and complete methods of programanalysis, and in particular static analysis by abstract interpretation and the generation of underapproximated formulae by symbolic execution*.
We are particularly interested in the combination of over- and sub-approximating abstractions, especially for memory. The priority applications envisaged concern the analysis of code at the binary level, as achieved by the combination of the BINSEC and CODEX analysis platforms, so as to automatically discover new security vulnerabilities, or prove their absence.
Embedded local blockchain on secure physical devices
The blockchain is based on a consensus protocol, the aim of which is to share and replicate ordered data between peers in a distributed network. The protocol stack, embedded in the network's peer devices, relies on a proof mechanism that certifies the timestamp and ensures a degree of fairness within the network.
The consensus protocols used in the blockchains deployed today are not suitable for embedded systems, as they require too many communication and/or computing resources for the proof. A number of research projects, such as IOTA and HashGraph, deal with this subject and will be analysed in the state of the art.
The aim of this thesis is to build a consensus protocol that is frugal in terms of communications and computing resources, and whose protocol stack will be implemented in a secure embedded device. This protocol must be based on the proof of elapsed time from our laboratory's work, which is also frugal, called Proof-of-Hardware-Time (PoHT), and must satisfy the properties of finality and fairness. The complete architecture of a peer node in the network will be designed and embedded on an electronic board including a microprocessor and several hardware security components, in such a way that the proof resource cannot be parallelized. Communication between peers will be established in a distributed manner.
Laser Fault Injection Physical Modelling in FD-SOI technologies: toward security at standard cells level on FD-SOI 10 nm node
The cybersecurity of our infrastructures is at the very heart in the digital transition on-going, and security must be ensured throughout the entire chain. At the root of trust lies the hardware, integrated circuits providing essential functions for the integrity, confidentiality and availability of processed information.
But hardware is vulnerable to physical attacks, and defence has to be organised. Among these attacks, some are more tightly coupled to the physical characteristics of the silicon technologies. An attack using a pulsed laser in the near infrared is one of them and is the most powerful in terms of accuracy and repeatability. Components must therefore be protected against this threat.
As the FD-SOI is now widely deployed in embedded systems (health, automotive, connectivity, banking, smart industry, identity, etc.) where security is required. FD-SOI technologies have promising security properties as being studied as less sensitive to a laser fault attack. But while the effect of a laser fault attack in traditional bulk technologies is well handled, deeper studies on the sensitivity of FD-SOI technologies has to be done in order to reach a comprehensive model. Indeed, the path to security in hardware comes with the modelling of the vulnerabilities, at the transistor level and extend it up to the standard cells level (inverter, NAND, NOR, Flip-Flop) and SRAM. First a TCAD simulation will be used for a deeper investigation on the effect of a laser pulse on a FD-SOI transistor. A compact model of an FD-SOI transistor under laser pulse will be deduced from this physical modelling phase. This compact model will then be injected into various standard cell designs, for two different objectives: a/ to bring the modelling of the effect of a laser shot to the level of standard cell design (where the analog behaviour of a photocurrent becomes digital) b/ to propose standard cell designs in FD-SOI 10nm technology, intrinsically secure against laser pulse injection. Experimental data (existing and generated by the PhD student) will be used to validate the models at different stages (transistor, standard cells and more complex circuits on ASIC).
Ce sujet de thèse est interdisciplinaire, entre conception microélectronique, simulation TCAD et simulation SPICE, tests de sécurité des systèmes embarqués. Le candidat sera en contact/encadré avec deux équipes de recherche; conception microélectronique , simulation TCAD et sécurité des systèmes embarqués.
Contacts: romain.wacquez@cea.fr, jean-frederic.christmann@cea.fr, sebastien.martinie@cea.fr
Dynamic Assurance Cases for Autonomous Adaptive Systems
Providing assurances that autonomous systems will operate in a safe and secure manner is a prerequisite for their deployment in mission-critical and safety-critical application domains. Typically, assurances are provided in the form of assurance cases, which are auditable and reasoned arguments that a high-level claim (usually concerning safety or other critical properties) is satisfied given a set of evidence concerning the context, design, and implementation of a system. Assurance case development is traditionally an analytic activity, which is carried out off-line prior to system deployment and its validity relies on assumptions/predictions about system behavior (including its interactions with its environment). However, it has been argued that this is not a viable approach for autonomous systems that learn and adapt in operation. The proposed PhD will address the limitations of existing assurance approaches by proposing a new class of security-informed safety assurance techniques that are continually assessing and evolving the safety reasoning, concurrently with the system, to provide through-life safety assurance. That is, safety assurance will be provided not only during initial development and deployment, but also at runtime based on operational data.