Artificial Intelligence (AI) increasingly powers safety-critical systems that demand robust, energy-efficient computation, often in environments marked by data scarcity and uncertainty. However, conventional AI approaches struggle to quantify confidence in their predictions, making them prone to unreliable or unsafe decisions.

This thesis contributes to the emerging field of Bayesian electronics, which exploits the intrinsic randomness of novel nanodevices to perform on-device Bayesian computation. By directly encoding probability distributions at the hardware level, these devices naturally enable uncertainty estimation while reducing computational overhead compared to traditional deterministic architectures.

Previous studies have demonstrated the promise of memristors for Bayesian inference. However, their limited endurance and high programming energy pose significant obstacles for on-chip learning applications.

This thesis proposes the use of ferroelectric memory field-effect transistors (FeMFETs)—which offer nondestructive readout and high endurance—as a promising alternative for implementing Bayesian neural networks.

This thrilling PhD position invites you to dive into the groundbreaking field of 2T0C (Two-Transistor, Zero-Capacitor) BEOL FET (Back-End-of-Line Field-Effect Transistor) based neurons and synapses, a revolutionary approach poised to transform neuromorphic computing. As a PhD student, you will be at the forefront of research that bridges advanced semiconductor technology with brain-inspired architectures, exploring how these innovative neuron circuits can emulate synaptic functions and enhance data processing efficiency.
Throughout this project, you will engage in hands-on design and characterization of cutting-edge 2T0C neuron circuits, utilizing state-of-the-art tools and techniques. You’ll collaborate with a dynamic, multidisciplinary team of engineers and researchers, tackling exciting challenges related to device performance and energy optimization.
Your work will involve extensive characterization of BEOL FET devices and circuits. You will have the opportunity to propose, specify and design new memory read architectures, that enables the exploration of multi-level synaptic behaviors toward the implementation of more energy and area efficient next-generation neuromorphic systems.
Join us for this unique opportunity to push the boundaries of technology and be part of a transformative journey that could redefine the future of computing! Your contributions could pave the way for breakthroughs in brain-inspired systems, making a lasting impact on the field.

As electronic architectures become increasingly complex and dense, managing thermal dissipation is a critical challenge to ensure system reliability and performance. In constrained environments and demanding applications, localized hotspots require innovative cooling solutions compatible with advanced packaging integrations such as 2.5D and 3D. This PhD project is part of this dynamic and aims to explore wafer-level thermal management approaches, relying in particular on advanced 3D integration processes such as direct bonding.

The PhD candidate will contribute to the design and fabrication of test vehicles incorporating temperature sensors and active thermal structures. The main objective will be to assess the efficiency of novel cooling architectures, with a particular focus on integrating microfluidic channels within the stacks, combined with the use of high thermal conductivity materials. The work will include aspects of thermal (and possibly thermo-mechanical) modeling, cleanroom process development, and experimental characterization.

This research topic, at the crossroads of microelectronics and thermal management, offers a stimulating and interdisciplinary framework, closely aligned with emerging industrial needs in advanced packaging.

This PhD offers a unique opportunity to enhance your skills in GaN power devices and develop cutting-edge architectures. You’ll work alongside a multidisciplinary team specializing in materials engineering, characterization, device simulation, and electrical measurements. If you’re eager to innovate, expand your knowledge, and tackle state-of-the-art challenges, this position is a valuable asset to your career!
Vertical GaN power components hold great promise for power applications beyond the kV range. Localized epitaxy of GaN enables the creation of thick structures on Si substrates at a competitive cost, with demonstrated success for diodes and pseudo-vertical transistors. However, this approach’s significant surface area limits the energy density of the devices. This PhD aims to develop denser, fully vertical components using layer transfer methods. You’ll study their electrical characteristics to monitor the impact of technological variations on their performance.
Throughout this PhD, you’ll gain comprehensive knowledge in microelectronics processes, electrical characterization, and TCAD (Technology Computer-Aided Design) simulation. You’ll collaborate with a multidisciplinary team including our partner CNRS-LTM and deepen your understanding of GaN power devices, all while being part of a lab dedicated to the development of wide-bandgap power devices. You will have the opportunity to write publications and patents.

With the rapid expansion of wireless networks and the imminent arrival of 6G, the need for highly efficient communication systems has never been more critical. In this context, frequencies beyond 140 GHz emerge as a key frontier, where cutting-edge technologies leverage advanced semiconductors like InP, delivering unmatched performance beyond what SiGe solutions can achieve. However, III-V components remain expensive, manufactured on small substrates (100 mm for InP), and incompatible with silicon production lines, which ensure higher industrial yields.
In this context, CEA-LETI, in collaboration with CNRS-LTM, is developing a new HBT transistor technology in which the base layer is made of antimonides, having already demonstrated frequency performance beyond the THz range. To enable integration with Si-CMOS fabrication processes, a novel approach for ohmic contact formation is required. This involves selective epitaxial regrowth of a suitable semiconductor material on the base layer of the HBT-GaAsSb transistor.
The PhD candidate will be responsible for identifying the optimal material that meets the required criteria, based on experiments conducted with the epitaxy team, advanced physical characterizations (ToF-SIMS, HR-TEM, EDX), and band structure modeling of the formed heterojunctions. This research will also be complemented by the fabrication of technological test structures to extract the key electrical parameters necessary for optimizing the DC and RF performance of the HBT transistor.