In-depth electrical and material characterization of low-K spacer
As part of the European Chip Act, CEA-Leti is pioneering a new generation of transistors using FDSOI architecture. Our goal is to deliver advanced performance with a strong emphasis on materials and energy efficiency. As we push the limits of planar transistors at 10 nm and 7 nm, we face significant physical challenges, particularly in reducing parasitic elements like capacitance and access resistance, which are critical for minimizing energy loss and optimizing performance. We are eager to tackle these challenges together.
We are excited to offer a unique PhD opportunity for motivated students interested in the field of semiconductor device engineering. Join our team to work on the incorporation and characterization of low-k spacer for advanced 7-10nm FDSOI Technology. This PhD offers the chance to work on a groundbreaking project. If you're curious, innovative, and eager for a challenge, this opportunity is perfect for you!
The impact of the dielectric spacer nature has relevant effects on the overall transistor performances, specifically in non-fully overlapped configuration. The dielectric spacer integration, optimization and engineering remains a challenge and becomes crucial to address technology advancement and scaling down demand. Numerous spacer candidates (SiN, SiCO, SiCON, SiCBN) have been introduced and identified as promising solutions, however, they frequently suffer from inherent defects and adverse electrical characteristics, such as charge trapping and presence of undesired interface states, which hinder their and the overall transistors performance.
Within this framework, the objective of this PhD is to conduct a comprehensive investigation and electrical characterization (CV,IV, BTI, HCI…) of the material spacer (interface, volume), providing an in-depth analysis of transistor performance and its underlying mechanisms. Innovative ultrafast CV stress-measurement characterization on dielectric samples will be also carried out and the correlation between trapping performance and the deposition parameters used in their fabrication will be established. Additionally, the candidate will collaborate closely with experts to contribute to the thin film deposition and characterization of new materials through surface analyses and thin-film characterizations (ellipsometry, FTIR, XRR, XPS…)
Throughout this journey, you will gain a broad spectrum of knowledge, spanning microelectronics materials and processes, analog integrated design, all while addressing the unique challenge of advance 7-10 nm FDSOI technology. You'll collaborate with multidisciplinary teams to develop a deep understanding of FDSOI devices and analyze existing and new measurements. You'll also be part of an integrated multidisciplinary lab, working alongside a team composed of several permanent researchers, exploring a wide range of research applications.
Artificial Intelligence for Integrated Electronics Design
As the technology fabrication processes improve towards nanometer-scale nodes, it is more and more complex to maintain the performance increase foreseen by Moore Law. To cope with this issue, technology processes provide various enhancing featuresi. More over, elementary components such as logic gates become legion. Providing a relevant design framework thus becomes a huge manual development task. As AI grows, it shows its skill to help decision making and hence components design, shaping a promising candidate to automate design flow. In this PhD subject, you will work on an AI model (LLM) capable of understanding electronic components. The works ultimately aim at developing a generation engine for electronic components.
Throughout this PhD, interdisciplinary research works will encompass a broad spectrum of knowledge around integrated electronics design, spanning microelectronics processes, electronic functions and logic gates implementation, neural networks architectures, large language models and generative AI.
Towards a low-resistive base contact for the InP-HBT transistor
Join CEA LETI for an exciting technological journey! Immerse yourself in the world of III V
based transistors integrated on compatible CMOS circuits for 6 G future communications
This thesis offers the chance to work on a ambitious project, with potential to continue into
a thesis If you're curious, innovative, and eager for a challenge, this opportunity is perfect
for you!
As the consumption of digital content continues to grow, we can foresee that 6 G
communication systems will have to find more capacity to support the increase in traffic
New Sub THz frequencies based systems are a huge opportunity to increase data rate but
are very challenging to build and maturate the power amplifier required to transmit a
signal will have to offer sufficient power and energy efficiency which is not obtained with
actual silicon technology InP based HBTs (Heterojunction Bipolar Transistors) developed
on large Silicon substrates have the potential to meet the requirements and be integrated
as close as possible to the CMOS circuits to enable minimal system/interconnect losses
Sb based semiconductors for GaAsSb HBT are emerging as highly promising materials,
especially for its electrical properties to integrate the Base layer of the Transistor It is
therefore necessary to produce high performance electrical contacts on this type of
semiconductor while remaining compatible with the manufacturing processes of the Si Fab
technology platforms
Throughout
this thesis, you will gain a broad spectrum of knowledge, beneficiate from the
rich technical environment of the 300 200 mm clean room and the nano characterization
platform You will collaborate with multidisciplinary teams to develop a deep understanding
of the ohmic contacts and analyse existing measurements Several apsects of the metal
(Ni or Ti p GaAs 1 x Sb x contact will be investigated
•Identify wet and plasma solutions allowing the GaAsSb native oxide removing without
damaging the surface with XPS and AFM
•Characterize GaAs 1 x Sb x epitaxy doping level (Hall effect, SIMS, TEM)
•Understand the phase sequence during annealing between the semiconductor and the
metal with XRD and Tof SIMS Manage this intermetallic alloys formation to not
deteriorate the contact interface (TEM image associated)
•Evaluate electrical contact properties using TLM structures Measurement of the
specific contact resistivity, sheet resistance of the semiconductor ant transfer length
associated The student will be a motive force to perform electrical tests on an automatic prober
architecture for embedded system of Automated and Reliable Mapping of indoor installations
The research focuses on the 3D localization of data from measurements inside buildings, where satellite location systems, such as GPS, are not operational. Different solutions exist in the literature, they rely in particular on the use of SLAM (Simultaneous Localization And Mapping) algorithms, but the 3D reconstruction is generally carried out a posteriori. In order to be able to propose this type of approach for embedded systems, a first thesis was carried out and led to a choice of algorithms to embed and a draft of the electronic architecture. A first proof of concept was also realized. Continuing this work, the thesis will have to propose a method allowing the localization device to be easily embedded on a wide range of nuclear measuring equipment (diameter, contamination meter, portable spectrometry, etc.). The work is not limited to a simple integration phase; it requires an architectural exploration, which will be based on adequacy between algorithm and architecture. These approaches will make it possible to respect different criteria, such as weight and small size so as not to compromise ergonomics for the operators carrying out the maps and quality of the reconstruction to ensure the reliability of the input data for the Digital Twin models.
Bayesian Neural Networks with Ferroelectric Memory Field-Effect Transistors (FeMFETs)
Artificial Intelligence (AI) increasingly powers safety-critical systems that demand robust, energy-efficient computation, often in environments marked by data scarcity and uncertainty. However, conventional AI approaches struggle to quantify confidence in their predictions, making them prone to unreliable or unsafe decisions.
This thesis contributes to the emerging field of Bayesian electronics, which exploits the intrinsic randomness of novel nanodevices to perform on-device Bayesian computation. By directly encoding probability distributions at the hardware level, these devices naturally enable uncertainty estimation while reducing computational overhead compared to traditional deterministic architectures.
Previous studies have demonstrated the promise of memristors for Bayesian inference. However, their limited endurance and high programming energy pose significant obstacles for on-chip learning applications.
This thesis proposes the use of ferroelectric memory field-effect transistors (FeMFETs)—which offer nondestructive readout and high endurance—as a promising alternative for implementing Bayesian neural networks.
Field Effect Transistor with Oxide Semiconductor Channel: Multi-Level Synaptic Functions and Analog Neurons
This thrilling PhD position invites you to dive into the groundbreaking field of 2T0C (Two-Transistor, Zero-Capacitor) BEOL FET (Back-End-of-Line Field-Effect Transistor) based neurons and synapses, a revolutionary approach poised to transform neuromorphic computing. As a PhD student, you will be at the forefront of research that bridges advanced semiconductor technology with brain-inspired architectures, exploring how these innovative neuron circuits can emulate synaptic functions and enhance data processing efficiency.
Throughout this project, you will engage in hands-on design and characterization of cutting-edge 2T0C neuron circuits, utilizing state-of-the-art tools and techniques. You’ll collaborate with a dynamic, multidisciplinary team of engineers and researchers, tackling exciting challenges related to device performance and energy optimization.
Your work will involve extensive characterization of BEOL FET devices and circuits. You will have the opportunity to propose, specify and design new memory read architectures, that enables the exploration of multi-level synaptic behaviors toward the implementation of more energy and area efficient next-generation neuromorphic systems.
Join us for this unique opportunity to push the boundaries of technology and be part of a transformative journey that could redefine the future of computing! Your contributions could pave the way for breakthroughs in brain-inspired systems, making a lasting impact on the field.
3D Hybrid Synapses for Energy-Efficient and Adaptive Edge AI
This PhD thesis is part of the growing field of embedded AI for the Internet of Things (IoT), where constraints in energy, area, and connectivity require rethinking the learning mechanisms of neural networks. The goal is to design neuromorphic architectures based on 3D hybrid synapses combining FeRAM and ReRAM, within an in-memory computing framework. The objective is to enable local adaptation of the model—drawing from machine learning approaches and potentially compatible with plasticity mechanisms such as STDP, VDSP, etc.—while maintaining efficient inference adapted to naturally asynchronous information. The PhD student will develop a heterogeneous memory architecture, design an appropriate local learning protocol, and implement integrated circuit demonstrators. Experimental validation on edge-relevant tasks (e.g., sensory classification) will assess power consumption, network accuracy, and adaptability. Publications and patents are expected outcomes of the thesis.
Innovative cooling solutions for 2.5D and 3D electronic systems
As electronic architectures become increasingly complex and dense, managing thermal dissipation is a critical challenge to ensure system reliability and performance. In constrained environments and demanding applications, localized hotspots require innovative cooling solutions compatible with advanced packaging integrations such as 2.5D and 3D. This PhD project is part of this dynamic and aims to explore wafer-level thermal management approaches, relying in particular on advanced 3D integration processes such as direct bonding.
The PhD candidate will contribute to the design and fabrication of test vehicles incorporating temperature sensors and active thermal structures. The main objective will be to assess the efficiency of novel cooling architectures, with a particular focus on integrating microfluidic channels within the stacks, combined with the use of high thermal conductivity materials. The work will include aspects of thermal (and possibly thermo-mechanical) modeling, cleanroom process development, and experimental characterization.
This research topic, at the crossroads of microelectronics and thermal management, offers a stimulating and interdisciplinary framework, closely aligned with emerging industrial needs in advanced packaging.
In-situ Monitoring of RF Power Amplifier Circuits Aging for Eco-design and Extended Lifetime
The semiconductor industry, and more specifically the radio-frequency (RF) circuit sector, is facing critical challenges related to eco-design and eco-innovation. These challenges include the need to extend the lifetime of circuits while meeting the growing demands of emerging markets such as 5G and the future 6G. Among these circuits, power amplifiers (PA) play a central role, being both critical components in terms of energy efficiency and key targets for improving robustness against aging and enabling potential reuse.
In this context, in-situ aging monitoring of PAs appears to be a promising approach for developing innovative and sustainable solutions. This research topic is therefore fully aligned with eco-design strategies, leveraging advanced technological platforms such as current and future CMOS SOI technologies, while integrating industrial constraints through existing strategic collaborations with major partners of CEA Leti.
This thesis aims to design an innovative in-situ monitoring solution to evaluate and compensate for the aging of power amplifiers, thereby extending their lifetime through reuse and self-correction strategies. To achieve this, it will rely on methodologies and circuits specifically adapted to practical use cases. The ambition is thus to develop a new generation of robust and durable circuits, integrating intelligent aging management mechanisms. By adopting an eco-design approach, this work aims to address environmental challenges while enhancing the industrial competitiveness of CMOS SOI technologies.
Reliability of RF GaN transistors for 5G millimeter Wave applications
Gallium Nitride components are very good candidates for power amplification at Millimeter Wave frequencies such as 5G (~30GHz), due to their power density and energy efficiency. However, these technologies are commonly integrated on Silicon Carbide substrates, which are thermally efficient but expensive and have small diameters. CEA-LETI's GaN/Si technology provides world-class performance in Ka band, with power densities competing with GaN/SiC technologies. These devices, fabricated on 200mm Si substrates, are compatible with Silicon clean rooms and promise greater available volumes and lower costs. Furthermore, the Silicon-like back-end levels offer possibilities for dense heterogeneous integration with digital circuits, paving the way towards heterogeneous RF Integrated Circuits (RFICs).
However, few studies exist nowadays on the degradation mechanisms tied to these specific components with CMOS-compatible process: advanced barriers, in-situ MIS gates, ohmic contacts, etc... It is mandatory to know and master these effects to qualify the technology as well as better understand the device weaknesses and limitations.
The goal of this PhD is to evaluate the parasitic memory effects as well as the transistor aging under operational conditions using DC and RF measurements, linked to the device physics. The transistors will be subjected to various electrical stress conditions to model their DC & RF degradation: trapping effects measurements (BTI, DCTS), influence of the process and gate technology (Schottky vs MIS), the electrical confinement inside the structure (GaN:C, AlGaN back-barrier, etc…). Time Dependent Dielectric Breakdown (TDDB) measurements will be made on MIS gates from DC to RF domain, to study the time to breakdown increase with input signal frequency, in a similar manner than gate dielectrics in CMOS devices. Finally, electrical stresses in DC and RF conditions (RF CW stresses) will be performed to evaluate and model the transistor degradation under operational conditions.