SiGe HBT LNA for cryogenic applications: design, characterization and optimization
The global race to build a quantum computer is heating up! These cutting-edge systems operate at temperatures below 4 K to preserve the delicate quantum states essential for computation. To achieve efficient control and detection, conventional electronic circuits must perform reliably at cryogenic temperatures, in close proximity to the quantum processor, thereby reducing wiring complexity and boosting performance. Beyond quantum computing, other domains—such as space exploration, high-performance computing, or high-energy physics—also require transistors capable of operating below 100 K.
During this phD, you will perform radiofrequency (RF) electrical characterization and modeling of Silicon-Germanium Heterojunction Bipolar Transistors in cryogenic environment, contributing to a deeper understanding of their behavior and optimizing their potential for extreme-condition applications. The objectives are twofold:
1.RF Electrical Characterization and Modeling:
•Conduct RF electrical measurements of SiGe HBTs at cryogenic temperatures.
•Develop accurate models to describe their behavior in cryogenic environments.
2.Optimization of Low-Noise Amplifiers (LNAs):
•Study the low-temperature behavior of individual passive and active devices composing an LNA.
•Optimize the design of low-noise amplifiers (LNAs) for cryogenic applications.
Study of mechanical stress on Solid State Micro-batteries
CEA-Leti provides integrated microstorage solutions, including solid state (or solid electrolyte) microbatteries. Solid-state micro-batteries are among the most promising microstorage technologies for applications in several fields such as the internet of things and implantable devices for medical use. The objective of this thesis is to study the impact of mechanical stresses on microbatteries, particularly during microbattery charge/discharge cycles. To this end, two approaches will be considered: experimental study with the development of mechanical test benches and numerical simulation.
The PhD student's work will begin with the development of test benches, the first of which will apply variable pressure to the surface of a microbattery during charge/discharge cycles. He/she will be required to develop the pressure measurement equipment. Once the mechanical test bench is operational, other characterizations, such as measuring anode deformations, will be considered. In parallel with this experimental work, a mechanical model will be developed. This model will be progressively refined using the experimental results obtained with the mechanical test bench, and new characterizations may be implemented in order to obtain the mechanical properties of the different materials used. Ultimately, the objective will be to propose the integration of new layers to improve the mechanical performance of microbatteries during cycling.
Dies to wafer direct bonding: from physical mechanisms to the development of thin stackable dies
Direct dies-to-wafer bonding has become, in recent years, a major development axis in microelectronics and at the heart of many LETI projects, both in silicon photonics and for 3D applications involving hybrid bonding.
Due to their small size, die bonding allows the study of direct bonding edge effects and the implementation of new direct bonding processes that can shed original light on the mechanisms of direct bonding, which are already well studied at LETI. From a more technological perspective, the development of thin stackable chips will also be a very interesting technological key for many applications. This approach is a clever alternative to classical damascene processes to address the challenges related to the planarization of surfaces with low density of high topographies.
Selective deposition of oxides by ALD
For next-generation microelectronics, Area Selective Deposition (ASD)is a promising approach to simplify integration schemes for the most advanced technology nodes. These ASD approaches need to be adapted according to a trio comprising the material to be deposited, the growth surface, and the inhibited surface.
This PhD focuses on the area selective deposition of oxides (such as SiO2, Al2O3, …) on Si or SiO2 and not on silicon nitride (SiN), which is one of the most complex topics in ASD, and aims to evaluate the relevance of this type of process for simplifying the integration and the fabrication of advanced FDSOI transistors.
To develop this selective oxide deposition process, various approaches aiming at making SiN an inhibitor of the Atomic Layer Deposition (ALD) will be explored (plasma treatments, Small Molecular Inhibitors, combination of both, etc.). Dedicated surface characterizations will be carried out in order to better understand the mechanisms of inhibition at the origin of the selective deposition and allowing to achieve high selectivity for oxide thicknesses of 10 nm and above.
This PhD project will take place at CEA-LETI, within the advanced materials deposition department, in collaboration with LMI UMR 5615 CNRS/UCBLyon. The student will have access to the CEA-LETI 300 mm cleanroom fabrication platforms for thin film deposition by PEALD, the CEA nanocharacterization platform and gas-phase surface functionalization at LMI. Surface analyses and thin film characterizations (ellipsometry, XRR, AFM, FTIR, contact angle, SEM, XPS, ToF-SIMS) will be used to determine the best selectivity and understand the physico-chemical mechanisms.
Integration of security functions for imagers: encryption, watermarking using compact functions close to the sensor
Illicit uses of images dramatically rise with deepfake content manipulation or unauthorized access. Securing images from their source i.e., at the image sensor level, is key to address the challenges of this field of cybersecurity. The "trusted imagers" addresses the need to ensure image security, authentication, and encryption starting at the point
of acquisition.
Building on our initial research, your PhD thesis will focus on finding innovative solutions to integrate security functions into image sensors with the challenge of meeting the requirements of low power consumption and compact integrated architecture, while keeping a high level of security. After an initial phase aiming at the development of the skills specific to the thesis, and depending on your background and interests, your work will involve:
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Developing encryption and/or watermarking algorithms in Python to evaluate their
complexity, then proposing compact versions compatible with integration into image
sensors.
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Evaluating the impact of algorithmic choices and hardware implementation on image
quality.
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Designing and validating hardware architectures that implement the algorithms.
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Designing the integrated circuits implementing these functions.
With the ultimate goal of fabricating an integrated circuit, the work will be conducted at CEA
Leti ,
using professional IC design tools and software development environments.
Development of vertical GaN power transistors gate module
This PhD topic offers a unique opportunity to enhance your skills in GaN power devices and develop cutting-edge architectures. You’ll work alongside a multidisciplinary team specializing in material engineering, characterization, device simulation, and electrical measurements. If you’re eager to innovate, expand your knowledge, and tackle state-of-the-art challenges, this position is a valuable asset to your career!
Vertical GaN power components are highly promising for applications beyond the kV range and are therefore extensively studied worldwide. Transistors with a 'trench MOSFET' architecture have been demonstrated in the state-of-the-art with very encouraging results. The gate stack of these devices is a crucial element as it directly impacts their on-state resistance, threshold voltage, and the control signal to be applied in a power converter. The proposed study will focus on developing innovative gate stacks that can withstand high gate voltages while maintaining state-of-the-art threshold voltage and channel mobility with minimal gate dielectric trapping. The work will involve studying the impact of process parameters on electrical characteristics. Special attention will be given to optimizing the gate geometry through TCAD simulations to study how its shape impacts on-state and breakdown. Identified improvements will be integrated to the devices fabricated on our 200mm GaN power devices line. The work will take place within the power devices lab and will be supported by several ongoing projects.
Study of Failure Modes and Mechanisms in RF Switches Based on Phase-Change Materials
Switches based on phase change materials (PCM) demonstrate excellent RF performance (FOM <10fs) and can be co-integrated into the BEOL of CMOS processes. However, their reliability is still very little studied today. Failure modes such as heater breakage, segregation, or the appearance of cavities in the material are shown during endurance tests, but the mechanisms of these failures are not discussed. The objective of this thesis will therefore be to study the failure modes and mechanisms for different operating conditions (endurance, hold, power). The analysis will be carried out through electrical and physical characterizations and accelerated aging methods will be implemented.
Design and test of a PLL in FD-SOI 28nm technology
The goal of this PhD thesis is to design a Phase Locked Loop for generic use at 5 GHz. This PLL will also include a study regarding each building bloc sensitivity to radiation and thermal sensitivity regarding space environment. This is the main point of this PhD thesis because integrating a PLL in harsh environment requires an accurate knowledge of the circuit's parameters. The candidate will begin its work by analysing existing works on the FD-SOI technology (structure characteristics and impact on radiation hardening) to serve as a base for its work and design a Phase Locked Loop architecture. He will also study how to characterise each PLL building bloc variations in harsh environment (radiation and temperature).
Superconducting Silicon and detection in the far Infrared Universe
Silicon technologies occupy a central position in today’s digital landscape, both for the fabrication of semiconductor devices and for the development of advanced sensors. In 2006, the discovery of superconductivity in silicon heavily doped with boron opened a new field of research. Since then, several laboratories, including CEA, have been investigating its electronic properties and potential applications. This emerging material exhibits particularly attractive characteristics for systems operating at sub-Kelvin cryogenic temperatures, especially in the fields of quantum electronics and ultra-sensitive detectors used in fundamental physics and astrophysics.
Despite these advances, the understanding of superconducting silicon remains incomplete, particularly regarding its thermal, mechanical, and optical properties at the micrometric scale. The proposed PhD aims to address these gaps by combining modelling, design, technological fabrication, and cryogenic characterization of prototype devices, within a close collaboration between CEA-Léti and CEA-Irfu. The main objective will be to develop a new generation of detectors based on this superconducting material and to demonstrate their relevance for the detection of electromagnetic radiation in the terahertz and far-infrared ranges.
Introduction of innovative materials for sub-10nm contact realization
As part of the FAMES project and the European ChipACT initiative, which aim to ensure France’s and Europe’s sovereignty and competitiveness in the field of electronic nano-components, CEA-LETI has launched the design of new FD-SOI chips. Among the various modules being developed, the fabrication of electrical contacts is one of the most critical modules in the success of advanced node development.
For sub-10 nm node, the contact realization is facing a lot of challenges like punchthrough (due to low etch selectivity during contact etching), voids during metal deposition, self-alignment, and parasitic capacitance. New breakthrough approach has recently been proposed consisting in the deposition of new dielectric films with chemical gradient. This thesis focuses on the development (deposition an etching processes) of new gradient compounds incorporated into SiO2 to address the current issues.