Topologically Isolated Mode Acoustic Resonators
Timing is a key function in electronic circuits. Beyond on-chip signals synchronization, it also allows the synchronization of wireless data transmissions. Accurate time references require stable frequency sources, which also benefit to sensor applications. The gold standard for time or frequency generation is still quartz resonators, which are however bulky and difficult to miniaturize. Research is therefore still ongoing to provide high quality factor (> 10,000) resonators, ideally capable of operating at frequencies of several GHz. A key to reach such high quality factors is to confine strongly the mechanical vibration of micro-size structures in order to make them insensitive to external perturbations. Recently, the field of topological acoustics has demonstrated the capability to confine elastic waves in very small volumes concentrated at the interface between periodic structure, and to provide extremely high quality factor resonances.
This PhD position focuses on exploiting topologically protected modes in piezoelectric microstructures to provide next generations of high quality factor resonators, which may be used in oscillators or even filter circuits. Leveraging the know-how of CEA Leti in the design and fabrication of such components, the PhD will be part of an international collaboration with well established academic laboratories (Politecnico di Milano, Imperial College FEMTO-ST Institute) and industrial partners.
The candidate will model and design structures supporting topologically protected modes, combinining finite element simulations with simplified numerical approaches which reduce computation times. He will follow the fabrication of demonstrators in collaboration with the process integration teams in the CEA Leti clean rooms, and carry on measurements of the proposed resonators.
Reinventing Microspeakers: From Planar Limits to 3D Designs for Ultrasonic Modulation Loudspeakers
Are you looking for a PhD at the intersection of acoustics, microsystems, and innovation? This project may be for you.This PhD focuses on the design, fabrication, and experimental validation of an innovative MEMS microspeaker concept based on ultrasound demodulation. Conventional micro transducers face a major limitation: they require large planar surfaces to displace sufficient air at low frequencies, leading to increased device size and manufacturing cost. This project explores an alternative architecture using vertical blade structures, exploiting the third dimension together with ultrasound demodulation to improve electro acoustic efficiency while reducing device footprint.
Building on preliminary exploratory work, the objective of the PhD is to develop a complete MEMS loudspeaker demonstrator. The work will include physical modeling, multi-physics simulation, device design optimization, microfabrication process development, and experimental electro acoustic characterization. Particular attention will be given to identifying and overcoming the physical and technological limitations governing device performance.
The candidate will design and simulate the device architecture and contribute to the definition of the fabrication process in close interaction with microfabrication specialists. The PhD work will also include acoustic and electrical characterization of the fabricated devices in order to validate the proposed concepts and compare experimental results with modeling predictions. The PhD will take place in a multidisciplinary environment, providing access to expertise in acoustics, MEMS design, microfabrication processes, and electro acoustic measurement.
Reliability and dynamic properties of GaN high electron mobility transistors : backbarrier and substrate type impact
The rapid expansion of AI and cloud computing has placed unprecedented demands on data center infrastructure, where energy efficiency is now a defining constraint. Despite their potential, many power systems still rely on silicon-based devices, which suffer from inherent efficiency limitations that result in significant energy losses. GaN HEMTs, with their superior electron mobility and high breakdown voltage, represent a compelling alternative, capable of achieving far higher efficiencies in power conversion. However, their broader adoption is constrained by reliability challenges, particularly those arising from charge trapping mechanisms that degrade device performance over time.
In this PhD project, you will delve into the fundamental dynamics of charge carriers in GaN HEMTs, focusing on the physical origins of on-resistance and threshold voltage drifts—key indicators of device instability. By systematically analyzing the electrical behavior of these transistors under various operating conditions, you will uncover the mechanisms behind their degradation and identify pathways to enhance their robustness. Your findings will directly inform the optimization of device architectures, enabling the development of more efficient and reliable power electronics that can meet the demands of modern data centers and beyond.
You will be part of a multidisciplinary research team at CEA-Leti, collaborating with experts in semiconductor material engineering, device simulation, and electrical characterization. This environment will provide you with a comprehensive skill set, spanning process engineering, advanced electrical testing, and TCAD simulations, This position will not only expand your expertise but also position you at the forefront of a field with global impact. By contributing to the advancement of GaN HEMTs, you will play a key role in shaping the future of power electronics—where innovation directly translates into sustainable technological solutions.
SiGe HBT LNA for cryogenic applications: design, characterization and optimization
The global race to build a quantum computer is heating up! These cutting-edge systems operate at temperatures below 4 K to preserve the delicate quantum states essential for computation. To achieve efficient control and detection, conventional electronic circuits must perform reliably at cryogenic temperatures, in close proximity to the quantum processor, thereby reducing wiring complexity and boosting performance. Beyond quantum computing, other domains—such as space exploration, high-performance computing, or high-energy physics—also require transistors capable of operating below 100 K.
During this phD, you will perform radiofrequency (RF) electrical characterization and modeling of Silicon-Germanium Heterojunction Bipolar Transistors in cryogenic environment, contributing to a deeper understanding of their behavior and optimizing their potential for extreme-condition applications. The objectives are twofold:
1.RF Electrical Characterization and Modeling:
•Conduct RF electrical measurements of SiGe HBTs at cryogenic temperatures.
•Develop accurate models to describe their behavior in cryogenic environments.
2.Optimization of Low-Noise Amplifiers (LNAs):
•Study the low-temperature behavior of individual passive and active devices composing an LNA.
•Optimize the design of low-noise amplifiers (LNAs) for cryogenic applications.
Study of mechanical stress on Solid State Micro-batteries
CEA-Leti provides integrated microstorage solutions, including solid state (or solid electrolyte) microbatteries. Solid-state micro-batteries are among the most promising microstorage technologies for applications in several fields such as the internet of things and implantable devices for medical use. The objective of this thesis is to study the impact of mechanical stresses on microbatteries, particularly during microbattery charge/discharge cycles. To this end, two approaches will be considered: experimental study with the development of mechanical test benches and numerical simulation.
The PhD student's work will begin with the development of test benches, the first of which will apply variable pressure to the surface of a microbattery during charge/discharge cycles. He/she will be required to develop the pressure measurement equipment. Once the mechanical test bench is operational, other characterizations, such as measuring anode deformations, will be considered. In parallel with this experimental work, a mechanical model will be developed. This model will be progressively refined using the experimental results obtained with the mechanical test bench, and new characterizations may be implemented in order to obtain the mechanical properties of the different materials used. Ultimately, the objective will be to propose the integration of new layers to improve the mechanical performance of microbatteries during cycling.
Dies to wafer direct bonding: from physical mechanisms to the development of thin stackable dies
Direct dies-to-wafer bonding has become, in recent years, a major development axis in microelectronics and at the heart of many LETI projects, both in silicon photonics and for 3D applications involving hybrid bonding.
Due to their small size, die bonding allows the study of direct bonding edge effects and the implementation of new direct bonding processes that can shed original light on the mechanisms of direct bonding, which are already well studied at LETI. From a more technological perspective, the development of thin stackable chips will also be a very interesting technological key for many applications. This approach is a clever alternative to classical damascene processes to address the challenges related to the planarization of surfaces with low density of high topographies.
Selective deposition of oxides by ALD
For next-generation microelectronics, Area Selective Deposition (ASD)is a promising approach to simplify integration schemes for the most advanced technology nodes. These ASD approaches need to be adapted according to a trio comprising the material to be deposited, the growth surface, and the inhibited surface.
This PhD focuses on the area selective deposition of oxides (such as SiO2, Al2O3, …) on Si or SiO2 and not on silicon nitride (SiN), which is one of the most complex topics in ASD, and aims to evaluate the relevance of this type of process for simplifying the integration and the fabrication of advanced FDSOI transistors.
To develop this selective oxide deposition process, various approaches aiming at making SiN an inhibitor of the Atomic Layer Deposition (ALD) will be explored (plasma treatments, Small Molecular Inhibitors, combination of both, etc.). Dedicated surface characterizations will be carried out in order to better understand the mechanisms of inhibition at the origin of the selective deposition and allowing to achieve high selectivity for oxide thicknesses of 10 nm and above.
This PhD project will take place at CEA-LETI, within the advanced materials deposition department, in collaboration with LMI UMR 5615 CNRS/UCBLyon. The student will have access to the CEA-LETI 300 mm cleanroom fabrication platforms for thin film deposition by PEALD, the CEA nanocharacterization platform and gas-phase surface functionalization at LMI. Surface analyses and thin film characterizations (ellipsometry, XRR, AFM, FTIR, contact angle, SEM, XPS, ToF-SIMS) will be used to determine the best selectivity and understand the physico-chemical mechanisms.
Integration of security functions for imagers: encryption, watermarking using compact functions close to the sensor
Illicit uses of images dramatically rise with deepfake content manipulation or unauthorized access. Securing images from their source i.e., at the image sensor level, is key to address the challenges of this field of cybersecurity. The "trusted imagers" addresses the need to ensure image security, authentication, and encryption starting at the point
of acquisition.
Building on our initial research, your PhD thesis will focus on finding innovative solutions to integrate security functions into image sensors with the challenge of meeting the requirements of low power consumption and compact integrated architecture, while keeping a high level of security. After an initial phase aiming at the development of the skills specific to the thesis, and depending on your background and interests, your work will involve:
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Developing encryption and/or watermarking algorithms in Python to evaluate their
complexity, then proposing compact versions compatible with integration into image
sensors.
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Evaluating the impact of algorithmic choices and hardware implementation on image
quality.
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Designing and validating hardware architectures that implement the algorithms.
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Designing the integrated circuits implementing these functions.
With the ultimate goal of fabricating an integrated circuit, the work will be conducted at CEA
Leti ,
using professional IC design tools and software development environments.
Development of vertical GaN power transistors gate module
This PhD topic offers a unique opportunity to enhance your skills in GaN power devices and develop cutting-edge architectures. You’ll work alongside a multidisciplinary team specializing in material engineering, characterization, device simulation, and electrical measurements. If you’re eager to innovate, expand your knowledge, and tackle state-of-the-art challenges, this position is a valuable asset to your career!
Vertical GaN power components are highly promising for applications beyond the kV range and are therefore extensively studied worldwide. Transistors with a 'trench MOSFET' architecture have been demonstrated in the state-of-the-art with very encouraging results. The gate stack of these devices is a crucial element as it directly impacts their on-state resistance, threshold voltage, and the control signal to be applied in a power converter. The proposed study will focus on developing innovative gate stacks that can withstand high gate voltages while maintaining state-of-the-art threshold voltage and channel mobility with minimal gate dielectric trapping. The work will involve studying the impact of process parameters on electrical characteristics. Special attention will be given to optimizing the gate geometry through TCAD simulations to study how its shape impacts on-state and breakdown. Identified improvements will be integrated to the devices fabricated on our 200mm GaN power devices line. The work will take place within the power devices lab and will be supported by several ongoing projects.
Study of Failure Modes and Mechanisms in RF Switches Based on Phase-Change Materials
Switches based on phase change materials (PCM) demonstrate excellent RF performance (FOM <10fs) and can be co-integrated into the BEOL of CMOS processes. However, their reliability is still very little studied today. Failure modes such as heater breakage, segregation, or the appearance of cavities in the material are shown during endurance tests, but the mechanisms of these failures are not discussed. The objective of this thesis will therefore be to study the failure modes and mechanisms for different operating conditions (endurance, hold, power). The analysis will be carried out through electrical and physical characterizations and accelerated aging methods will be implemented.