3D assembly of GaN power devices

The increase in electrical power density in everyday uses is the result of technological developments including materials and components. The first element to address is the use of a semiconductor material suitable for strong integration and capable of managing high power densities. Since the 2010s, wide bandgap semiconductors such as SiC or GaN have emerged in several applications and are causing a revolution in power electronics design, notably with an increase in the operating frequency and specific power of converters. Concerning Galium nitride (GaN), the increase in switching frequency was made possible thanks to the HEMT (High Electron Mobility Transistor).
The idea of ??this PhD topic is to work on a HEMT GaN cell assembly. The work will involve the an assembly of two components through a common electrode on their backsides in order, making it possible to reduce parasitic inductances and increase the operating frequency. The work will be based on simulation tools such as COMSOL and Synopsys. The thesis will be in collaboration with the GEEPS laboratory at CentraleSupelec and the University of Paris-Saclay.

Advanced fully-depleted Silicon-on-insulator devices for Radio-Frequency applications

The PhD will be performed in the NEXTGEN project aimed at developing the next generation of Silicon-on-insulator devices. Our laboratory is driving the development of the RF active devices: this is a great opportunity to carry out fundamental research using state-of-the art processing equipment and characterization instruments while working in close collaboration with our industrial partners.

you will expected to engage in tasks encompassing:
- perform back-of the-envelope estimation of device properties and assess performace impact of technological choices
- Perform and/or analyze TCAD simulations to gain insight in the RF device behaviour
- data-mining on engineering measurements: grasp the relevant information and identify trends or correlations
- perform extensive periods of time in the lab to conduct or participate in on-wafer RF characterization champaign.
Based on you profile or expectations, above tasks may be dynamically rebalanced during the thesis.

Stocastic integrated power supplies based on emerging components

Context:
The widespread utilization of connected devices that process sensitive information necessitates the creation of new secure systems. The prevalent attack, referred to as power side-channel, involves the retrieval of encryption key information by analyzing the power consumption of the system. Integrating the system with its power supply management blocks can conceal the consumption of sensitive blocks, especially by utilizing various techniques to introduce randomized variations during power transfer. The CEA has wide experience in the design and testing of secure integrated circuits and it is exploring a new approach to DC-DC conversion that uses emerging devices available at CEA-Léti.
The work of the PhD researcher will be the following:
- Specification of integrated power supplies using switched-capacitor architecture.
- Study the circuit using emerging components and evaluate the improvement of its robustness against side channel attacks.
- Design of the integrated power supply in silicon technology.
- Performance and security characterization of the designed blocks and security primitives in
their whole.
The division of labor is 10% advanced study, 20% system architecture, 50% circuit design, 20% experimental measurement.

Laser Fault Injection Physical Modelling in FD-SOI technologies: toward security at standard cells level on FD-SOI 10 nm node

The cybersecurity of our infrastructures is at the very heart in the digital transition on-going, and security must be ensured throughout the entire chain. At the root of trust lies the hardware, integrated circuits providing essential functions for the integrity, confidentiality and availability of processed information.
But hardware is vulnerable to physical attacks, and defence has to be organised. Among these attacks, some are more tightly coupled to the physical characteristics of the silicon technologies. An attack using a pulsed laser in the near infrared is one of them and is the most powerful in terms of accuracy and repeatability. Components must therefore be protected against this threat.
As the FD-SOI is now widely deployed in embedded systems (health, automotive, connectivity, banking, smart industry, identity, etc.) where security is required. FD-SOI technologies have promising security properties as being studied as less sensitive to a laser fault attack. But while the effect of a laser fault attack in traditional bulk technologies is well handled, deeper studies on the sensitivity of FD-SOI technologies has to be done in order to reach a comprehensive model. Indeed, the path to security in hardware comes with the modelling of the vulnerabilities, at the transistor level and extend it up to the standard cells level (inverter, NAND, NOR, Flip-Flop) and SRAM. First a TCAD simulation will be used for a deeper investigation on the effect of a laser pulse on a FD-SOI transistor. A compact model of an FD-SOI transistor under laser pulse will be deduced from this physical modelling phase. This compact model will then be injected into various standard cell designs, for two different objectives: a/ to bring the modelling of the effect of a laser shot to the level of standard cell design (where the analog behaviour of a photocurrent becomes digital) b/ to propose standard cell designs in FD-SOI 10nm technology, intrinsically secure against laser pulse injection. Experimental data (existing and generated by the PhD student) will be used to validate the models at different stages (transistor, standard cells and more complex circuits on ASIC).
Ce sujet de thèse est interdisciplinaire, entre conception microélectronique, simulation TCAD et simulation SPICE, tests de sécurité des systèmes embarqués. Le candidat sera en contact/encadré avec deux équipes de recherche; conception microélectronique , simulation TCAD et sécurité des systèmes embarqués.

Contacts: romain.wacquez@cea.fr, jean-frederic.christmann@cea.fr, sebastien.martinie@cea.fr

Secure Hardware/Software Implementation of Post-Quantum Cryptography on RISC-V Platforms

Traditional public-key cryptography algorithms are considered broken when a large-scale quantum computer is successfully realized. Consequently, the National Institute of Standards and Technology (NIST) in the USA has launched an initiative to develop and standardize new Post-Quantum Cryptography (PQC) algorithms, aiming to replace established public-key mechanisms. However, the adoption of PQC algorithms in Internet of Things (IoT) and embedded systems poses several implementation challenges, including performance degradation and security concerns arising from the potential susceptibility to physical Side-Channel Attacks (SCAs).
The idea of this Ph.D. project is to explore the modularity, extensibility and customizability of the open-source RISC-V ISA with the goal of proposing innovative, secure and efficient SW/HW implementations of PQC algorithms. One of the main challenge related to the execution of PQC algorithms on embedded processors is to achieve good performance (i.e. low latency and high throughput) and energy efficiency while incorporating countermeasures against physical SCAs. In the first phase, the Ph.D. candidate will review the State-Of-the-Art (SoA) with the objective of understanding weaknesses and attack points of PQC algorithms, the effectiveness and overhead of SoA countermeasures, and SoA acceleration strategies. In the second phase, the candidate will implement new solutions by exploiting all degrees of freedom offered by the RISC-V architecture and characterize the obtained results in terms of area overhead, execution time and resistance against SCAs.
Beyond the exciting scientific challenges, this PhD will take place in Grenoble, a picturesque city nestled in the French Alps. The research will be conducted at the CEA, in LETI and LIST institutes, and in collaboration with the TIMA laboratory.

Design of FD-SOI-specific True Random Number Generator

TRNGs are the essential block of any cryptographic system. Current standards, such as AIS-31, require a stochastic model, which directly relates the model of the physical source of randomness to the entropy of the generated random bits. TRNGs are benchmarked based on their throughput, efficiency and robustness. As such, FD-SOI (Fully Depleted Silicon on Insulator) is a technology well known for its advantages in terms of consumption, but also for the adaptability of its characteristics granted by its unique back bias control acting as a second gate.
This PhD position aims to extend the use of this back gate by studying the opportunities offered by an integrated management of the back gate. By applying a voltage, the BOX allows the adjustment of characteristics at a transistor level. This technique called back biasing, enables the fine-tuning of characteristics and has thus far not been used in the design of security primitives. This technique will be implemented for a FD-SOI specific TRNG based on coherent sampling. Though the novelty and the relevance of the FD-SOI based approach is clear, and motivations to go toward coherent sampling architectures for TRNG have been documented in the literature, the objective of the PhD student will be to bring experimental demonstration, with the support of simulation and modelling of these specific architectures. This will be made possible by a first version of ASIC samples already available at the start of the PhD and the design (by the PhD student) of another ASIC.

Lithography process and design rules co-optimisation for advance microelectronics

Historically, the development of integrated circuit performance has been based on the reduction in size of individual components. The main driving force behind this miniaturization is photolithography, a key step in the semiconductor component manufacturing process. This process consists in reproducing the design of the circuits to be produced in a photosensitive resin. These complex patterns are generated in a single exposure. Light from an ultra-low-wavelength light source (DeepUV) projects a mask image onto the resin. The higher the optical resolution, the greater the miniaturization of the circuits.

When developing new technologies in microelectronics (e.g. FDSOI 10nm, advanced photonics), it is necessary to establish circuit design rules and in parallel to develop photolithography processes to reproduce these designs on the chip. The aim of this thesis is to build bridges between these 2 distinct but closely interwoven worlds, in order to co-optimize their development.

Starting from a practical case for advanced technologies, the thesis work will address the following areas/problems:
- Improving the accuracy and cycle time of the digital lithography models calibration needed to correct optical proximity effects (OPC);
- Using CD-SEM characterizations, identifying borderline design configurations and adjusting design rule constraints accordingly;
- Designing innovative patterns that optimize the dimensional space covered, and evaluating them with a rigorous lithography simulation tool and/or experimentally;
- Integrating lithography results into design tools to establish causal links with device electrical performance.

The thesis will be carried out in Grenoble, at CEA-Leti, internationally recognized for the excellence of its research in the field of microelectronics, and will benefit from the exceptional facilities of the institute's clean room. In particular, the student will be attached to the Laboratoire de PAtterning Computationnel (LPAC), which is exploring ways of improving lithography and etching processes by relying heavily on digital tools, in close partnership with a number of major industrial players. The lab brings together around fifteen people from a wide range of complementary backgrounds (Masters students, student engineers, PhD students, technicians, engineers and researchers, on fixed-term or permanent contracts), who are used to working closely together to give everyone the chance to fulfil their potential and contribute collectively to the progress of the laboratory's work.
The student will be expected to publish and share his/her work at various international conferences.

Development and characterization of embedded memories based on ferroelectric transistors for neuromorphic applications

As part of CEA-LETI's Devices for Memory and Computation Laboratory (LDMC), you will be working on the development and optimization of FeFET transistors with amorphous oxide semiconductor channels for neuromorphic applications and near-memory computing.
The main challenge when co-integrating semiconductor and ferroelectric oxides is to perfectly assess and control a proper amount of oxygen vacancies, which govern both the ferroelectric properties of HfZrO2 and the conduction properties of semiconducting oxide, and impose major constraints on the manufacturing process steps.
The aim of the proposed internship is to conduct electrical measurements on various kind of elementary devices, stand-alone ferroelectric / semiconductive oxide films up to complete integreted FeFET devices. This will allow to propose an optimized process flow capable to provide both efficient ferroelectric switching performances (speed, low voltage capability…) together with state-of-the-art MOSFET performances (Ion/Ioff, subthreshold slope…).
The student will have access to a large amount of processed 200mm wafers, embedding a large variety of FeFET device flavors with different dimensions. Different process options will be available, either on already-available wafers or on request during the internship. For the latter, this will involve a close interaction with process experts (either deposition, annealing...) for modifying the FeFET process flow.
The student will benefit from state-of-the-art characterization platform, either for material characterization (XPS, UPS, XRD, TEM microscopy…) or for measuring the FeFET electrical performances.

Ultra-compact electronic actuation of micro-UAVs

Reducing the size of electronic systems for micro-drones is crucial for decreasing their weight, extending their battery life, and enhancing their maneuverability. This doctoral project aims to explore innovative solutions for energy management in integrated circuits designed for high-voltage actuation of micro-motors for very small drones (weighing about one gram and measuring a few mm³). The project encompasses micromechanics, the use of new small batteries developed by CEA-Leti, and the application of advanced microelectronic technologies. Through a collaboration between Gaël Pillonnet (CEA) and Patrick Mercier (University of California, San Diego - UCSD), you will benefit from a research environment at the forefront of technology, focused on the design of integrated circuits, and more specifically, on power management circuits (Power Management IC, PMIC). This work offers an exciting applicative dimension, with the integration of the circuit and batteries into an ultra-compact assembly intended for the activation of micro-motors. By joining our team, you will contribute to the advancement of cutting-edge technologies that will have a significant impact on the micro-drone sector.

architecture for embedded system of Automated and Reliable Mapping of indoor installations

The research focuses on the 3D localization of data from measurements inside buildings, where satellite location systems, such as GPS, are not operational. Different solutions exist in the literature, they rely in particular on the use of SLAM (Simultaneous Localization And Mapping) algorithms, but the 3D reconstruction is generally carried out a posteriori. In order to be able to propose this type of approach for embedded systems, a first thesis was carried out and led to a choice of algorithms to embed and a draft of the electronic architecture. A first proof of concept was also realized. Continuing this work, the thesis will have to propose a method allowing the localization device to be easily embedded on a wide range of nuclear measuring equipment (diameter, contamination meter, portable spectrometry, etc.). The work is not limited to a simple integration phase; it requires an architectural exploration, which will be based on adequacy between algorithm and architecture. These approaches will make it possible to respect different criteria, such as weight and small size so as not to compromise ergonomics for the operators carrying out the maps and quality of the reconstruction to ensure the reliability of the input data for the Digital Twin models.

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