Embedded local blockchain on secure physical devices
The blockchain is based on a consensus protocol, the aim of which is to share and replicate ordered data between peers in a distributed network. The protocol stack, embedded in the network's peer devices, relies on a proof mechanism that certifies the timestamp and ensures a degree of fairness within the network.
The consensus protocols used in the blockchains deployed today are not suitable for embedded systems, as they require too many communication and/or computing resources for the proof. A number of research projects, such as IOTA and HashGraph, deal with this subject and will be analysed in the state of the art.
The aim of this thesis is to build a consensus protocol that is frugal in terms of communications and computing resources, and whose protocol stack will be implemented in a secure embedded device. This protocol must be based on the proof of elapsed time from our laboratory's work, which is also frugal, called Proof-of-Hardware-Time (PoHT), and must satisfy the properties of finality and fairness. The complete architecture of a peer node in the network will be designed and embedded on an electronic board including a microprocessor and several hardware security components, in such a way that the proof resource cannot be parallelized. Communication between peers will be established in a distributed manner.
Combined Software and Hardware Approaches for Large Scale Sparse Matrix Acceleration
Computational physics, artificial intelligence and graph analytics are important compute problems which depend on processing sparse matrices of huge dimensions. This PhD thesis focuses on the challenges related to efficiently processing such sparse matrices, by applying a systematic software are hardware approach.
Although the processing of sparse matrices has been studied from a purely software perspective for decades, in recent years many dedicated, and very specific hardware, accelerators for sparse data have been proposed. What is missing is a vision of how to properly exploit these accelerators, as well as standard hardware such as GPUs, to efficiently solve a full problem. Prior to solving a matrix problem, it is common to perform pre-processing of the matrix. This can include techniques to improve the numerical stability, to adjust the form of the matrix, and techniques to divide it into smaller sub-matrices (tiling) which can be distributed to processing cores. In the past, this pre-processing has assumed homogenous compute cores. New approaches are needed, to take advantage of heterogeneous cores which can include dedicated accelerators and GPUs. For example, it may make sense to dispatch the sparsest regions to specialized accelerators and to use GPUs for the denser regions, although this has yet to be shown. The purpose of this PhD thesis is to take a broad overview of the processing of sparse matrices and to analyze what software techniques are required to exploit existing and future accelerators. The candidate will build on an existing multi-core platform based on RISC-V cores and an open-source GPU to develop a full framework and will study which strategies are able to best exploit the available hardware.
ALD materials for FE and AFE capacitances
Ultrathin HfO2-based materials are regarded as promising candidates for embedded non-volatile memory (eNVM) and logic devices. The CEA-LETI has a leadership position in the field of BEOL-FeRAM memories ultra-low consumption (<100fj/bit) at low voltage (<1V). In this context, the developments expected in this thesis aim to evaluate the impact of HfO2-based ferroelectric FE and antiferroelectric AFE layers (10 to 4 nm fabricated by Atomic Layer Deposition ALD) on the FeRAM properties and performances.
In particular, the subject will permit a deep understanding of the crystallographic phases governing the FE/AFE properties using advanced measurements techniques offered by the CEA-LETI nano-characterization platform (physico-chemical, structural and microscopy analysis, electrical measurements). Several integration solutions for ferroelectric capacitances FeCAPs using ALD FE/AFE layers will be studied including doping, interface layers, sequential fabrication w/wo air break…
Thus, the developments based on FeCAPs stack fabricated using 300mm ALD deposition tool aspires to explore the following items:
1-Doping incorporation in FE/AFE layers (La, Y…)
2-Engineering of the interface between FE/AFE layers and top/bottom electrode
3-Plasma in-situ treatment of bottom electrode surface
4-Sequential deposition with and without air break
[1] S. Martin et al. – IEDM 2024
[2] Appl. Phys. Lett. 124, 243508 (2024)
PRObablistic on-edge learning for SPINtronic-based neuromorphic systems
The hired joint UGA – KIT PHD candidate should be able to cover the work of the workpackage 1 and 2. He/she will also participate to technical meetings and have a good understanding on how the tasks of the other technical workpackages are executed, mainly by the partners with internal effort. As a whole, the PHD candidate will develop and optimize compact Computing in Memory architectures, provide high level models for further integration in large scale designs, perform validation of all proofs of concepts of new architectural implementations. He/she will be involved also in the design of algorithmic implementations of Bayesian Neural Networks adapted to the architecture. More in details, he/she will work on the following directions:
Design and optimization of the probabilistic neural networks, will be executed mostly in SPINTEC Laboratory in Grenoble, that will include:
1. full design stack of hardware accelerator without selector transistor for frequent Read and Write operations.
2. Design and validate an innovative architectural approach able to compensate for sneaky paths phenomena.
3. High-level modeling of the full crossbar architecture that includes the stochastic component.
4. Propose a full simulation and validation flow scalable to scaled to realistic architecture size and parameters that implement Bayesian tasks.
5. Perform Delay, power consumption and area overhead figures of merit
SCO&FE ALD materials for FeFET transistors
Ferroelectric Field Effect Transistors FeFET is a valuable high-density memory component suitable for 3D DRAM. FeFET concept combines oxide semiconductors SCO as canal material and ferroelectric metal oxides FE as transistor gate [2, 3]. Atomic layer deposition ALD of SCO and FE materials at ultrathin thickness level (<10 nm) and low temperature (10 cm2.Vs); ultrathin (<5nm) and ultra-conformal (aspect ratio 1:10). The PhD student will beneficiate from the rich technical environment of the 300/200mm CEA-LETI clean-room and the nano-characterization platform (physico-chemical, structural and microscopy analysis, electrical measurements).
The developments will focus on the following items:
1-Comparison of SCO layers (IGZO Indium Gallium Zinc Oxide) fabricated using ALD and PVD techniques: implementation of adapted mesurements techniques and test vehicles
2-Intrinsec and electrical characterization of ALD-SCO (IWO, IGZO, InO) and ALD-EF (HZO) layers: stoichiometry, structure, resistivity, mobility….
3-Co-integration of ALD-SCO and ALD-FE layers for vertical and horizontal 3D FeFET structures
[1]10.35848/1347-4065/ac3d0e
[2]https://doi.org/10.1109/TED.2023.3242633
[3]https://doi.org/10.1021/acs.chemmater.3c02223
Laser Fault Injection Physical Modelling in FD-SOI technologies: toward security at standard cells level on FD-SOI 10 nm node
The cybersecurity of our infrastructures is at the very heart in the digital transition on-going, and security must be ensured throughout the entire chain. At the root of trust lies the hardware, integrated circuits providing essential functions for the integrity, confidentiality and availability of processed information.
But hardware is vulnerable to physical attacks, and defence has to be organised. Among these attacks, some are more tightly coupled to the physical characteristics of the silicon technologies. An attack using a pulsed laser in the near infrared is one of them and is the most powerful in terms of accuracy and repeatability. Components must therefore be protected against this threat.
As the FD-SOI is now widely deployed in embedded systems (health, automotive, connectivity, banking, smart industry, identity, etc.) where security is required. FD-SOI technologies have promising security properties as being studied as less sensitive to a laser fault attack. But while the effect of a laser fault attack in traditional bulk technologies is well handled, deeper studies on the sensitivity of FD-SOI technologies has to be done in order to reach a comprehensive model. Indeed, the path to security in hardware comes with the modelling of the vulnerabilities, at the transistor level and extend it up to the standard cells level (inverter, NAND, NOR, Flip-Flop) and SRAM. First a TCAD simulation will be used for a deeper investigation on the effect of a laser pulse on a FD-SOI transistor. A compact model of an FD-SOI transistor under laser pulse will be deduced from this physical modelling phase. This compact model will then be injected into various standard cell designs, for two different objectives: a/ to bring the modelling of the effect of a laser shot to the level of standard cell design (where the analog behaviour of a photocurrent becomes digital) b/ to propose standard cell designs in FD-SOI 10nm technology, intrinsically secure against laser pulse injection. Experimental data (existing and generated by the PhD student) will be used to validate the models at different stages (transistor, standard cells and more complex circuits on ASIC).
Ce sujet de thèse est interdisciplinaire, entre conception microélectronique, simulation TCAD et simulation SPICE, tests de sécurité des systèmes embarqués. Le candidat sera en contact/encadré avec deux équipes de recherche; conception microélectronique , simulation TCAD et sécurité des systèmes embarqués.
Contacts: romain.wacquez@cea.fr, jean-frederic.christmann@cea.fr, sebastien.martinie@cea.fr
Sub-10nm CMOS performances assessment by co-optimization of lithography and design
While developing and introducing new technologies (ex. FDSOI 10nm CMOS), design rules (DRM) are the guidelines used to ensure that a chip design can be reliably fabricated. These rules govern the physical dimensions and spacing of various features used by the designer in the chip layout. They translate both device electrical constraints and manufacturing processes constraints. Among them, lithography and patterning processes are critical step in defining the intricate structures and features on a semiconductor wafer. The most efficient design rules can only be obtained from a co-optimization merging design and lithography constraints.
The objective of this research work is to demonstrate that the use of a digital lithography twin can improve the performance of CMOS by co-optimization of design and lithography (DTCO).
Starting from specific use cases for FDSOI 10nm CMOS technologies, and using advanced lithography simulation tools, the candidate would :
- Develop novel characterization methods to assess lithography process capabilities (hotspot prediction).
- Assess design rules with respect to the lithography process capabilities.
- Quantify, though design rules, lithography impact on device performances.
- Identify significant both process and design limitations and propose paths to challenge them.
As PhD student of CEA-Leti, you will join a technology research institute dedicated to micro and nanotechnologies, within a dynamic and international research environment. You will join the Computational Patterning Laboratory with strong connections with integrated circuit design experts of CEA-Leti. You will benefit from the exceptional facilities of the institute's 300mm clean room and from state-of-the art lithography software tools.
You will be encouraged to publish your work and participate to international conferences and workshops.
Water at the hydrophilic direct bonding interface
The microelectronics industry is making increasing use of hydrophilic direct bonding technology to produce innovative substrates and components. CEA LETI's teams have been leaders in this field for over 20 years, offering scientific and technological studies on the subject.
The key role of water at the bonding interface can be newly understood thanks to a characterization technique developed at CEA LETI. The aim of this thesis is to confirm or refute the physico-chemical mechanisms at play at the bonding interface, depending on the surface preparations and materials in contact.
A large part of this work will be carried out on our cleanroom tools. The characterization of surface hydration using this original technique will be complemented by standard characterizations such as adhesion and adherence energy measurements, FTIR-MIR and SIMS analyses, and X-ray reflectivity at ESRF.
Scalable NoC-based Programmable Cluster Architecture for future AI applications
Context
Artificial Intelligence (AI) has emerged as a major field impacting various sectors, including healthcare, automotive, robotics, and more. Hardware architectures must now meet increasingly demanding requirements in terms of computational power, low latency, and flexibility. Network-on-Chip (NoC) technology is a key enabler in addressing these challenges, providing efficient and scalable interconnections within multiprocessor systems. However, despite its benefits, designing NoCs poses significant challenges, particularly in optimizing latency, energy consumption, and scalability.
Programmable cluster architectures hold great promise for AI as they enable resource adaptation to meet the specific needs of deep learning algorithms and other compute-intensive AI applications. By combining the modularity of clusters with the advantages of NoCs, it becomes possible to design systems capable of handling ever-increasing AI workloads while ensuring maximum energy efficiency and flexibility.
Summary of the Thesis Topic
This PhD project aims to design a scalable, programmable cluster architecture based on a Network-on-Chip tailored for future AI applications. The primary objective will be to design and optimize a NoC architecture capable of meeting the high demands of AI applications in terms of intensive computing and efficient data transfer between processing clusters.
The research will focus on the following key areas:
1. NoC Architecture Design: Developing a scalable and programmable NoC to effectively connect various AI processing clusters.
2. Performance and Energy Efficiency Optimization: Defining mechanisms to optimize system latency and energy consumption based on the nature of AI workloads.
3. Cluster Flexibility and Programmability: Proposing a modular and programmable architecture that dynamically allocates resources based on the specific needs of each AI application.
4. Experimental Evaluation: Implementing and testing prototypes of the proposed architecture to validate its performance on real-world use cases, such as image classification, object detection, and real-time data processing.
The outcomes of this research may contribute to the development of cutting-edge embedded systems and AI solutions optimized for the next generation of AI applications and algorithms.
The work performed during this thesis will be presented at international conferences and scientific journals. Certain results may be patented.
Wideband Hybrid Transmitter for Future Wireless Systems
This research is part of an effort to reduce the energy consumption and carbon footprint of future wireless systems by investigating innovative transmitter (TX) architectures with improved energy efficiency. Objective of the thesis is to elaborate a novel TX architecture for beyond 5G and 6G standards. Efficiency enhancement design techniques such as supply modulation or load modulation have been proposed in the past to improve TX efficiency, but the increasing requirement in terms of instantaneous bandwidth tends to limit the benefit of those techniques. During the thesis, the candidate will develop a novel integrated hybrid TX architecture that combine load and supply modulation. On particular, she/he will develop a dedicated co-design methodology between the power amplifier and the supply modulator in order to address 6G-FR3 bands (10GHz+) with high PAPR (>10dB) and high bandwidth (>200MHz) signals.
The candidate will join the integrated radiofrequency architecture laboratory where various skill (system, IC design and layout …) and field of expertise are represented (RF power, Low power RF, RF sensors, High-speed mmW). During the thesis, she/he will analyze and model new TX architectures, perform IC and package design, including layout, to achieve and validate hardware demonstrators.
link:
http://www.leti-cea.com/cea-tech/leti/english/Pages/Applied-Research/Facilities/Integration-Platform.aspx
https://www.youtube.com/watch?v=da3x89qxCHM
We are looking for this type of profile:
• MSc or Engineering degree in electronics or microelectronics
• Knowledge in transistor technology (CMOS, Bipolar, GaN…) and Analog/RF design
• Experience in ADS or/and Cadence
• Basic programming skills (Python, Matlab …)
• First experience in IC design is an asset
Contact: Guillaume.robe@cea.fr, Pascal.reynier@cea.fr
Key words : Power amplifier, Load modulation, Supply modulator, RF module.