Integration of security functions for imagers: encryption, watermarking using compact functions close to the sensor
Illicit uses of images have dramatically risen with deepfake content manipulation or unauthorized access. Securing images at their source i.e., at the image sensor level, is key to addressing the challenges of this field of cybersecurity. The "trusted imagers" concept addresses the need to ensure image security, authentication, and encryption starting at the point of acquisition.
Building on our initial research, notably regarding the in-situ generation of keys, your PhD thesis will focus on finding innovative solutions to integrate security functions into image sensors with the challenge of meeting the requirements of low power consumption and compact integrated architecture, while keeping a high level of security. After an initial phase aiming at the development of the skills specific to the thesis, and depending on your background and interests, your work will involve:
- Developing encryption and/or watermarking algorithms in Python to evaluate their complexity, then proposing compact versions compatible with integration into image sensors.
- Evaluating the impact of algorithmic choices and hardware implementation on image quality.
- Designing and validating hardware architectures that implement the algorithms.
- Designing the integrated circuits implementing these functions.
With the ultimate goal of fabricating an integrated circuit, the work will be conducted at CEA-Leti, using professional IC design tools and software development environments.
Development of vertical GaN power transistors gate module
This PhD topic offers a unique opportunity to enhance your skills in GaN power devices and develop cutting-edge architectures. You’ll work alongside a multidisciplinary team specializing in material engineering, characterization, device simulation, and electrical measurements. If you’re eager to innovate, expand your knowledge, and tackle state-of-the-art challenges, this position is a valuable asset to your career!
Vertical GaN power components are highly promising for applications beyond the kV range and are therefore extensively studied worldwide. Transistors with a 'trench MOSFET' architecture have been demonstrated in the state-of-the-art with very encouraging results. The gate stack of these devices is a crucial element as it directly impacts their on-state resistance, threshold voltage, and the control signal to be applied in a power converter. The proposed study will focus on developing innovative gate stacks that can withstand high gate voltages while maintaining state-of-the-art threshold voltage and channel mobility with minimal gate dielectric trapping. The work will involve studying the impact of process parameters on electrical characteristics. Special attention will be given to optimizing the gate geometry through TCAD simulations to study how its shape impacts on-state and breakdown. Identified improvements will be integrated to the devices fabricated on our 200mm GaN power devices line. The work will take place within the power devices lab and will be supported by several ongoing projects.
Study of Etching Mechanisms in Dielectric Materials: Application to Low Global Warming Potential Gases
Interconnection levels (Back-End Of Line, or BEOL) in microelectronics enable the connection of transistors to achieve the desired device functionalities. The fabrication of these levels relies on lithography and plasma etching processes. Plasma dry etching is a key technique in the manufacturing of microelectronic devices, as it allows the precise definition of structures at the nanometer scale. This process involves several major challenges, including stringent control of etch profiles, critical dimensions of the patterns, and the assurance of selectivity between different materials. Beyond these technical aspects, plasma etching also raises significant environmental concerns. Indeed, the gases used in these processes, such as fluorocarbons, are often greenhouse gases with very high global warming potential (GWP).
The objective is therefore twofold: to reduce the carbon footprint of these processes while maintaining, or even improving, the critical post-etch performance metrics, such as achieving the target critical dimensions, avoiding damage to the etched materials, preventing defect formation, and ensuring the spatial uniformity of these performances
Reliability and dynamic properties of GaN high electron mobility transistors : backbarrier and substrate type impact
The rapid expansion of AI and cloud computing has placed unprecedented demands on data center infrastructure, where energy efficiency is now a defining constraint. Despite their potential, many power systems still rely on silicon-based devices, which suffer from inherent efficiency limitations that result in significant energy losses. GaN HEMTs, with their superior electron mobility and high breakdown voltage, represent a compelling alternative, capable of achieving far higher efficiencies in power conversion. However, their broader adoption is constrained by reliability challenges, particularly those arising from charge trapping mechanisms that degrade device performance over time.
In this PhD project, you will delve into the fundamental dynamics of charge carriers in GaN HEMTs, focusing on the physical origins of on-resistance and threshold voltage drifts—key indicators of device instability. By systematically analyzing the electrical behavior of these transistors under various operating conditions, you will uncover the mechanisms behind their degradation and identify pathways to enhance their robustness. Your findings will directly inform the optimization of device architectures, enabling the development of more efficient and reliable power electronics that can meet the demands of modern data centers and beyond.
You will be part of a multidisciplinary research team at CEA-Leti, collaborating with experts in semiconductor material engineering, device simulation, and electrical characterization. This environment will provide you with a comprehensive skill set, spanning process engineering, advanced electrical testing, and TCAD simulations, This position will not only expand your expertise but also position you at the forefront of a field with global impact. By contributing to the advancement of GaN HEMTs, you will play a key role in shaping the future of power electronics—where innovation directly translates into sustainable technological solutions.
Integrated optical functions on microbolometer focal planes for uncooled infrared imaging
Thermal infrared imaging (wavelengths 8-14 µm) is a growing field, particularly in industry, transportation, and environment. It relies on a detection technology, microbolometers, for which CEA-Leti is at the forefront of the global state of the art. Integrating advanced optical functions directly onto the detectors is a very promising approach for improving performance, compactness, and cost in future infrared cameras.
The optical functions under consideration include spectral filtering, polarimetry, wavefront correction, and more. Some aim to enrich the image with information essential for applications such as absolute thermography (temperature and emissivity measurement), identification for automated scene interpretation (machine vision), gas detection, and others.
The proposed work will include the design, fabrication, and electro-optical characterization of functionalized microbolometer arrays. Using 3D electromagnetic simulation tools, the design of these optical functions will take into account the compatibility with our microbolometer technologies and the capabilities of our microfabrication facilities. Fabrication will take place in the CEA-Leti cleanrooms by dedicated personnel, but the candidate will participate in defining and monitoring the work. Finally, optical and electro-optical characterizations will be performed in our laboratory, if necessary with the development of dedicated characterization benches.
Introduction of innovative materials for sub-10nm contact realization
As part of the FAMES project and the European ChipACT initiative, which aim to ensure France’s and Europe’s sovereignty and competitiveness in the field of electronic nano-components, CEA-LETI has launched the design of new FD-SOI chips. Among the various modules being developed, the fabrication of electrical contacts is one of the most critical modules in the success of advanced node development.
For sub-10 nm node, the contact realization is facing a lot of challenges like punchthrough (due to low etch selectivity during contact etching), voids during metal deposition, self-alignment, and parasitic capacitance. New breakthrough approach has recently been proposed consisting in the deposition of new dielectric films with chemical gradient. This thesis focuses on the development (deposition an etching processes) of new gradient compounds incorporated into SiO2 to address the current issues.
Investigation and Modeling of Ferroelectric and Antiferroelectric Domain Dynamics in HfO2-Based Capacitors
The proposed PhD work lies within the exploration of new supercapacitor and hybrid energy storage technologies, aiming to combine miniaturization, high power density, and CMOS process compatibility. The hosting laboratory (LTEI/DCOS/LCRE) has recognized expertise in thin-film integration and dielectric material engineering, offering unique opportunities to investigate ferroelectric (FE) and antiferroelectric (AFE) behaviors in doped hafnium oxide (HfO2).
The thesis will focus on the experimental investigation and physical modeling of thin-film HfO2-based capacitors, intentionally doped to exhibit ferroelectric or antiferroelectric properties depending on the composition and deposition conditions (for instance, through ZrO2 or SiO2 doping). Such materials are particularly attractive for realizing devices that combine non-volatile memory and energy storage functions on a single CMOS-compatible platform, enabling ultra-low-power autonomous systems such as edge computing architectures, environmental sensors, and smart connected objects.
The research will involve the fabrication and characterization of metal–insulator–metal (MIM) capacitors based on doped HfO2 integrated on silicon substrates. Systematic electrical measurements—including current–voltage (I–V) and polarization–electric field (P–E) characterizations—will be carried out under various frequencies, amplitudes, and cycling conditions to investigate the relaxation mechanisms of FE and AFE domains. Analysis of minor hysteresis loops will provide access to the distribution of activation energies and enable the modeling of domain relaxation dynamics. A physical model will be developed or refined to describe FE/AFE transitions under cyclic electrical excitation, incorporating effects such as charge trapping, mechanical stress, and domain nucleation kinetics.
The overall objective is to optimize the recoverable energy density and the energy conversion efficiency of these capacitors, while establishing design guidelines for compact, efficient, and silicon-integrable energy storage devices. The insights gained from this work will contribute to a deeper understanding of the dynamic mechanisms governing FE/AFE behavior in doped HfO2, with potential impact on ferroelectric memories, energy-harvesting devices, and low-power neuromorphic architectures.
Design and test of a PLL in FD-SOI 28nm technology
The goal of this PhD thesis is to design a Phase Locked Loop for generic use at 5 GHz. This PLL will also include a study regarding each building bloc sensitivity to radiation and thermal sensitivity regarding space environment. This is the main point of this PhD thesis because integrating a PLL in harsh environment requires an accurate knowledge of the circuit's parameters. The candidate will begin its work by analysing existing works on the FD-SOI technology (structure characteristics and impact on radiation hardening) to serve as a base for its work and design a Phase Locked Loop architecture. He will also study how to characterise each PLL building bloc variations in harsh environment (radiation and temperature).