Reducing damage and loading in high aspect ratio III-V etching
The growing demand for III-V semiconductors in high-efficiency photovoltaics, quantum photonics, and advanced imaging technologies requires innovative and cost-effective fabrication methods. This PhD project focuses on developing plasma etching processes for In-based III-V semiconductors to produce high aspect ratio (HAR) structures on large wafers from 100 to 300 mm. The research addresses two key challenges: understanding how etching process windows evolve with material loading and process conditions (physical vs. chemical dominance), and minimizing electrical degradation induced by HAR etching, which is critical for device performance.
These challenges are fundamentally linked to the low volatility of In-based etch byproducts, the need to balance kinetic and thermal energy inputs to enhance etch selectivity, and the management of etch loading effects for large-scale production. The experimental approach will leverage CEA-Leti's state-of-the-art facilities, including the Photonics platform for 2–4-inch wafer processing, which enables masking strategies (hard mask deposition, photolithography) and low-temperature (150°C) etching.
Characterization will involve SEM for etch profile analysis, XPS for surface composition, and TEM-EDX for sidewall quality assessment. Damage evaluation will be performed using near-infrared photoluminescence decay to measure minority carrier lifetime and identify recombination centers. The work aims to develop optimized HAR etching processes (aspect ratios >10, critical dimensions <1 µm) for In-based III-V materials, investigate pulsed plasma techniques to reduce etch-induced damage, and provide insights into defect formation mechanisms to guide process optimization for industrial applications.
Introduction of innovative materials for sub-10nm contact realization
As part of the FAMES project and the European ChipACT initiative, which aim to ensure France’s and Europe’s sovereignty and competitiveness in the field of electronic nano-components, CEA-LETI has launched the design of new FD-SOI chips. Among the various modules being developed, the fabrication of electrical contacts is one of the most critical modules in the success of advanced node development.
For sub-10 nm node, the contact realization is facing a lot of challenges like punchthrough (due to low etch selectivity during contact etching), voids during metal deposition, self-alignment, and parasitic capacitance. New breakthrough approach has recently been proposed consisting in the deposition of new dielectric films with chemical gradient. This thesis focuses on the development (deposition an etching processes) of new gradient compounds incorporated into SiO2 to address the current issues.
Advanced electrode materials by ALD for ionic devices
This work aims to develop Advanced ultrathin cunductive layers (<10nm) by ALD (Atomic Layer Deposition)for électrodes use(resistivity 100). The other challenge aims to reduce the ALD-based electrode layer thickness less than 5nm while still maintaining the advanced electric properties (resistivity in the mOhm range).
This work covers multiple aspects including inter alia ALD process, ALD precursors, Elementary characterization of intrinsec properties (physico-chemical, morphological and electrochemical) as well as integration on short loop 3D devices.
Superconducting silicide contacts on hyperdoped silicon by nanosecond pulsed-laser annealing
In the race towards building a quantum computer, there is a deep interest in fabricating devices based on the robust and scalable silicon FD-SOI technology. One example is the Josephson Field Effect Transistor (JoFET) whose operability relies on the high transparency of the interface between the superconducting source/drain regions and the semiconducting channel. Such transparency could be improved by doping the source/drain regions, and hence lowering the Schottky barrier height at the superconductor/semiconductor interfaces.
This PhD aims at developing highly transparent superconducting silicide contacts on a 300 mm production line using Nanosecond Pulsed Laser Annealing (NPLA). NPLA will play a key role for reaching extremely high doping concentrations in silicon [1,2], then forming the superconducting silicides (CoSi2, V3Si) with minimal thermal budget and related dopant deactivation. A particular focus will be devoted on the stresses during silicide formation and their impact on the superconducting critical temperature. Also, the distribution of dopants will be assessed by Atom Probe Tomography (APT), an advanced 3D imaging technique capable of imaging the distribution of dopants at the atomic scale [3]. Finally, electrical measurements on fabricated junctions and transistors will be carried out at low temperature (< 1 K) in order to evaluate the transparency of the superconducting contacts.
New generation of organic susbtrates for power conversion
Recent advances in electric motors and associated power electronics have led to a significant increase in power density requirements. This increase in power density means smaller heat exchange surfaces, which amplifies the challenges associated with dissipating the heat generated by power electronics components during operation. In fact, the lack of adequate heat dissipation causes electronic components to overheat, impacting their performance, durability, and reliability. Other issues related to cost, repairability, and thermomechanical constraints call into question traditional ceramic-based insulating thermal interfaces. It is therefore imperative to develop a new generation of heat-dissipating materials that take the system environment into account.
The objective of this thesis is to replace the ceramic substrate in power module systems, whose main role is to act as the system's dielectric layer, with a thermally conductive organic matrix composite. The current substrate has well-known limitations (fragility, poor interface, cycling limit, cost). The organic substrate must have the highest possible thermal conductivity (>3 W/m.k) in order to dissipate the heat emitted properly, while also being electrically insulating with a breakdown voltage of approximately 3kV/mm. It must also have a coefficient of thermal expansion (CTE) compatible with that of copper in order to eliminate delamination phenomena during the cycling undergone by the device during its lifetime. The innovation of the doctoral student's work will lie in the use of highly thermally conductive (nano)fillers that will be electrically insulated (insulating coating) and can be oriented in a polymer resin under external stimulus.
The development of the electrical insulating shell on the thermally conductive core will be carried out using the sol-gel method. The synthesis will be controlled and optimized in order to correlate the homogeneity and thickness of the coating with the dielectric and thermal performance of the (nano)composite. The charge/matrix interface (a potential source of phonon diffraction) will also be studied. A second part will focus on grafting magnetic nanoparticles (MNPs) onto thermally conductive (nano)fillers. Commercial MNPs will be evaluated (depending on requirements, grades synthesized in the laboratory may also be evaluated). The (nano)composites must have rheology compatible with pressing and/or injection processes.
Effect of gamma-ray irradiation on ferroelectric, hafnia-based, non-volatile memory for use in extreme environments
The emergence of hafnia-based ferroelectric (FE) memories has opened a new paradigm for ultra-low-power edge computing. Hafnia is fully compatible with CMOS technology and is ultra low-power—three orders of magnitude less than other emerging memory technologies.
These advantages align with strategic applications in space, defense, medical, nuclear safety, and heavy-duty transport, where electronics face harsh radiation environments.
Imprint induces a shift of the Polarization-Voltage (P-V) curve along the voltage axis and is attributed to charge trapping/detrapping, domain pinning and charged defects. All may be accentuated under irradiation.
The project will use advanced photoelectron spectroscopy techniques including synchrotron radiation induced Hard X-ray photoelectron spectroscopy and complementary structural analysis including high-resolution electron microscopy, X-ray diffraction and near field microscopy. The experimental characterization will be accompanied by theoretical calculations to simulate the material response to irradiation
The work will be carried out in the framework of close collaboration between the CEA/Leti in Grenoble providing the samples, integrated devices and wafer scale characterization and the CEA/Iramis in Saclay for the fundamental analysis of the material properties, irradiation experiments and device scale characterizations.
Integrated material–process–device co-optimization for the design of high-performance RF transistors on advanced nanometer technologies
This PhD research focuses on the integrated co-optimization of materials, fabrication processes and device architectures to enable high-performance RF transistors on advanced nanometer-scale technologies. The work aims to understand and improve key RF figures of merit—such as transit frequency, maximum oscillation frequency, noise behaviour and linearity—by establishing clear links between material choices, process innovations and transistor design.
The project combines experimental development, structural and electrical characterization, and advanced TCAD simulations to analyse the strengths and limitations of different integration schemes, including FD-SOI and emerging 3D architectures such as GAA and CFET. Particular attention will be given to the engineering of optimized spacers, gate stacks, junction placement and epitaxial source/drain materials in order to minimize parasitic effects and enhance RF efficiency.
By comparing planar and 3D device platforms within a unified modelling and characterization framework, the thesis aims to provide technology guidelines for future generations of energy-efficient RF transistors targeting applications in 5G/6G communications, automotive radar and low-power IoT systems.
III-V semiconductor nanoplatelets
Colloidal semiconductor nanoplatelets (NPLs) are a class of two-dimensional nanostructures that have electronic and optical properties distinct from those of spherical quantum dots (QDs). They exhibit strong quantum confinement in a single dimension, their thickness, which can be controlled on the monolayer level using solution chemistry. As a result, NPLs emit light with an extremely narrow spectral width and at the same time, they have a very high absorption coefficients. These properties make them ideal candidates for various applications (e.g., light-emitting diodes for low-power-consumption displays, photocatalysis, single-photon emitters).
At present, only the synthesis of metal chalcogenide NPLs has been mastered. These materials either contain toxic elements (CdSe, HgTe, etc.) or have a large bandgap (ZnS, ZnSe). For these reasons, the development of synthesis methods for III-V semiconductor NPLs, such as InP, InAs and InSb is currently a major challenge. In this thesis, we will develop new synthetic approaches for the growth of InP NPLs, exploring different avenues and using in situ characterizations as well as machine learning assisted design of experiments. Numerical simulations will be used to determine the reactivity of precursors and to model the mechanisms inducing anisotropic growth.
Modeling and characterization of CFET transistors for enhanced electrical performance
Complementary Field Effect Transistors (CFETs) represent a new generation of vertically stacked CMOS devices, offering a promising path to continue transistor miniaturization and to meet the requirements of high-performance computing.
The objective of this PhD work is to study and optimize the strain engineering of the transistor channel in order to enhance carrier mobility and improve the overall electrical performance of CFET devices. The work will combine numerical modeling of technological processes using finite element methods with experimental characterization of crystalline deformation through transmission electron microscopy coupled with precession electron diffraction (TEM-PED).
The modeling activity will focus on predicting strain distributions and their impact on electrical properties, while accurately accounting for the complexity of the technological stacks and critical fabrication steps such as epitaxy. In parallel, the experimental work will aim to quantify strain fields using TEM-PED and to compare these results with simulation outputs.
This research will contribute to the development of dedicated modeling tools and advanced characterization methodologies adapted to CFET architectures, with the goal of improving spatial resolution, measurement reproducibility, and the overall understanding of strain mechanisms in next-generation transistors.
Investigation and Modeling of Ferroelectric and Antiferroelectric Domain Dynamics in HfO2-Based Capacitors
The proposed PhD work lies within the exploration of new supercapacitor and hybrid energy storage technologies, aiming to combine miniaturization, high power density, and CMOS process compatibility. The hosting laboratory (LTEI/DCOS/LCRE) has recognized expertise in thin-film integration and dielectric material engineering, offering unique opportunities to investigate ferroelectric (FE) and antiferroelectric (AFE) behaviors in doped hafnium oxide (HfO2).
The thesis will focus on the experimental investigation and physical modeling of thin-film HfO2-based capacitors, intentionally doped to exhibit ferroelectric or antiferroelectric properties depending on the composition and deposition conditions (for instance, through ZrO2 or SiO2 doping). Such materials are particularly attractive for realizing devices that combine non-volatile memory and energy storage functions on a single CMOS-compatible platform, enabling ultra-low-power autonomous systems such as edge computing architectures, environmental sensors, and smart connected objects.
The research will involve the fabrication and characterization of metal–insulator–metal (MIM) capacitors based on doped HfO2 integrated on silicon substrates. Systematic electrical measurements—including current–voltage (I–V) and polarization–electric field (P–E) characterizations—will be carried out under various frequencies, amplitudes, and cycling conditions to investigate the relaxation mechanisms of FE and AFE domains. Analysis of minor hysteresis loops will provide access to the distribution of activation energies and enable the modeling of domain relaxation dynamics. A physical model will be developed or refined to describe FE/AFE transitions under cyclic electrical excitation, incorporating effects such as charge trapping, mechanical stress, and domain nucleation kinetics.
The overall objective is to optimize the recoverable energy density and the energy conversion efficiency of these capacitors, while establishing design guidelines for compact, efficient, and silicon-integrable energy storage devices. The insights gained from this work will contribute to a deeper understanding of the dynamic mechanisms governing FE/AFE behavior in doped HfO2, with potential impact on ferroelectric memories, energy-harvesting devices, and low-power neuromorphic architectures.