Development of ultra-high-resolution magnetic microcalorimeters for isotopic analysis of actinides by X-ray and gamma-ray spectrometry
The PhD project focuses on the development of ultra-high-resolution magnetic microcalorimeters (MMCs) to improve the isotopic analysis of actinides (uranium, plutonium) by X- and gamma-ray spectrometry around 100 keV. This type of analysis, which is essential for the nuclear fuel cycle and non-proliferation efforts, traditionally relies on HPGe detectors, whose limited energy resolution constrains measurement accuracy. To overcome these limitations, the project aims to employ cryogenic MMC detectors operating at temperatures below 100 mK, capable of achieving energy resolutions ten times better than that of HPGe detectors. The MMCs will be microfabricated at CNRS/C2N using superconducting and paramagnetic microstructures, and subsequently tested at LNHB. Once calibrated, they will be used to precisely measure the photon spectra of actinides in order to determine the fundamental atomic and nuclear parameters of the isotopes under study with high accuracy. The resulting data will enhance the nuclear and atomic databases used in deconvolution codes, thereby enabling more reliable and precise isotopic analysis of actinides.
In situ study of the impact of the electric field on the properties of chalcogenide materials
Chalcogenide materials (PCM, OTS, NL, TE, FESO, etc.) are the basis of the most innovative concepts in microelectronics, from PCM memories to the new neuromorphic and spinorbitronic devices (FESO, SOT-RAM, etc.). Part of their operation relies on out-of-equilibrium physics induced by the electronic excitation resulting from the application of an intense electric field. The aim of this thesis is to measure experimentally on chalcogenide thin films the effects induced by the intense electric field on the atomic structure and electronic properties of the material with femtosecond (fs) time resolution. The 'in-operando' conditions of the devices will be reproduced using a THz fs pulse to generate electric fields of the order of a few MV/cm. The induced changes will then be probed using various in situ diagnostic methods (optical spectroscopy or x-ray diffraction and/or ARPES). The results will be compared with ab initio simulations using a state-of-the-art method developed with the University of Liège. Ultimately, the ability to predict the response of different chalcogenide alloys on time scales fs under extreme field conditions will make it possible to optimise the composition and performance of the materials (e- switch effect, electromigration of species under field conditions, etc.), while providing an understanding of the underlying fundamental mechanisms linking electronic excitation, evolution and the properties of the chalcogenide alloys.
In-depth electrical and material characterization of low-K spacer
As part of the European Chip Act, CEA-Leti is pioneering a new generation of transistors using FDSOI architecture. Our goal is to deliver advanced performance with a strong emphasis on materials and energy efficiency. As we push the limits of planar transistors at 10 nm and 7 nm, we face significant physical challenges, particularly in reducing parasitic elements like capacitance and access resistance, which are critical for minimizing energy loss and optimizing performance. We are eager to tackle these challenges together.
We are excited to offer a unique PhD opportunity for motivated students interested in the field of semiconductor device engineering. Join our team to work on the incorporation and characterization of low-k spacer for advanced 7-10nm FDSOI Technology. This PhD offers the chance to work on a groundbreaking project. If you're curious, innovative, and eager for a challenge, this opportunity is perfect for you!
The impact of the dielectric spacer nature has relevant effects on the overall transistor performances, specifically in non-fully overlapped configuration. The dielectric spacer integration, optimization and engineering remains a challenge and becomes crucial to address technology advancement and scaling down demand. Numerous spacer candidates (SiN, SiCO, SiCON, SiCBN) have been introduced and identified as promising solutions, however, they frequently suffer from inherent defects and adverse electrical characteristics, such as charge trapping and presence of undesired interface states, which hinder their and the overall transistors performance.
Within this framework, the objective of this PhD is to conduct a comprehensive investigation and electrical characterization (CV,IV, BTI, HCI…) of the material spacer (interface, volume), providing an in-depth analysis of transistor performance and its underlying mechanisms. Innovative ultrafast CV stress-measurement characterization on dielectric samples will be also carried out and the correlation between trapping performance and the deposition parameters used in their fabrication will be established. Additionally, the candidate will collaborate closely with experts to contribute to the thin film deposition and characterization of new materials through surface analyses and thin-film characterizations (ellipsometry, FTIR, XRR, XPS…)
Throughout this journey, you will gain a broad spectrum of knowledge, spanning microelectronics materials and processes, analog integrated design, all while addressing the unique challenge of advance 7-10 nm FDSOI technology. You'll collaborate with multidisciplinary teams to develop a deep understanding of FDSOI devices and analyze existing and new measurements. You'll also be part of an integrated multidisciplinary lab, working alongside a team composed of several permanent researchers, exploring a wide range of research applications.
Interface physics of ferroelectric AlBN/Ga2O3 and AlBN/GaN stacks for power electronics
Commercial aviation accounts for about 2.5% total world CO2 emissions (1bT). A true, long-term, clean perspective eliminating a significant part of CO2 emissions is electric. One viable solution could be the hybrid airplane in which gas turbines are used for take-off and landing and in-flight cruising is electrically powered. Such a solution requires high voltage components. Fundamental research is required to optimize materials for integration into electronic components, capable of sustaining these power ratings.
The original idea of the Ferro4Power proposal is to increase the range of applications of Ga2O3 and GaN based devices by introducing a high breakdown, power electronics compatible, ferroelectric layer into the device stack. The up or down polarization state of the ferroelectric layer will provide an electric field capable of modulating the Ga2O3 and GaN valence and conduction bands, and hence the properties of possible devices, such as Schottky diodes (SBD), hybrid depletion mode transistors for Ga2O3 and high frequency HEMTs for GaN. Our hypothesis is to control the electronic bands of Ga2O3 and GaN using an adjacent AlBN.
We will explore the chemistry and electronic structure of AlBN/Ga2O3 and AlBN/GaN interfaces, focusing on the key phenomena of polarization screening, charge trapping/dissipation, internal fields. The project will use advanced photoelectron spectroscopy techniques including synchrotron radiation induced Hard X-ray photoelectron spectroscopy and Photoemission electron microscopy as well as complementary structural analysis including high-resolution electron microscopy, X-ray diffraction and near field microscopy.
The results should therefore be of interest to both physicists studying fundamental aspects of functionality in artificial heterostructures and engineers working in R & D applications of power electronics.
Towards a low-resistive base contact for the InP-HBT transistor
Join CEA LETI for an exciting technological journey! Immerse yourself in the world of III V
based transistors integrated on compatible CMOS circuits for 6 G future communications
This thesis offers the chance to work on a ambitious project, with potential to continue into
a thesis If you're curious, innovative, and eager for a challenge, this opportunity is perfect
for you!
As the consumption of digital content continues to grow, we can foresee that 6 G
communication systems will have to find more capacity to support the increase in traffic
New Sub THz frequencies based systems are a huge opportunity to increase data rate but
are very challenging to build and maturate the power amplifier required to transmit a
signal will have to offer sufficient power and energy efficiency which is not obtained with
actual silicon technology InP based HBTs (Heterojunction Bipolar Transistors) developed
on large Silicon substrates have the potential to meet the requirements and be integrated
as close as possible to the CMOS circuits to enable minimal system/interconnect losses
Sb based semiconductors for GaAsSb HBT are emerging as highly promising materials,
especially for its electrical properties to integrate the Base layer of the Transistor It is
therefore necessary to produce high performance electrical contacts on this type of
semiconductor while remaining compatible with the manufacturing processes of the Si Fab
technology platforms
Throughout
this thesis, you will gain a broad spectrum of knowledge, beneficiate from the
rich technical environment of the 300 200 mm clean room and the nano characterization
platform You will collaborate with multidisciplinary teams to develop a deep understanding
of the ohmic contacts and analyse existing measurements Several apsects of the metal
(Ni or Ti p GaAs 1 x Sb x contact will be investigated
•Identify wet and plasma solutions allowing the GaAsSb native oxide removing without
damaging the surface with XPS and AFM
•Characterize GaAs 1 x Sb x epitaxy doping level (Hall effect, SIMS, TEM)
•Understand the phase sequence during annealing between the semiconductor and the
metal with XRD and Tof SIMS Manage this intermetallic alloys formation to not
deteriorate the contact interface (TEM image associated)
•Evaluate electrical contact properties using TLM structures Measurement of the
specific contact resistivity, sheet resistance of the semiconductor ant transfer length
associated The student will be a motive force to perform electrical tests on an automatic prober
Bayesian Neural Networks with Ferroelectric Memory Field-Effect Transistors (FeMFETs)
Artificial Intelligence (AI) increasingly powers safety-critical systems that demand robust, energy-efficient computation, often in environments marked by data scarcity and uncertainty. However, conventional AI approaches struggle to quantify confidence in their predictions, making them prone to unreliable or unsafe decisions.
This thesis contributes to the emerging field of Bayesian electronics, which exploits the intrinsic randomness of novel nanodevices to perform on-device Bayesian computation. By directly encoding probability distributions at the hardware level, these devices naturally enable uncertainty estimation while reducing computational overhead compared to traditional deterministic architectures.
Previous studies have demonstrated the promise of memristors for Bayesian inference. However, their limited endurance and high programming energy pose significant obstacles for on-chip learning applications.
This thesis proposes the use of ferroelectric memory field-effect transistors (FeMFETs)—which offer nondestructive readout and high endurance—as a promising alternative for implementing Bayesian neural networks.
Field Effect Transistor with Oxide Semiconductor Channel: Multi-Level Synaptic Functions and Analog Neurons
This thrilling PhD position invites you to dive into the groundbreaking field of 2T0C (Two-Transistor, Zero-Capacitor) BEOL FET (Back-End-of-Line Field-Effect Transistor) based neurons and synapses, a revolutionary approach poised to transform neuromorphic computing. As a PhD student, you will be at the forefront of research that bridges advanced semiconductor technology with brain-inspired architectures, exploring how these innovative neuron circuits can emulate synaptic functions and enhance data processing efficiency.
Throughout this project, you will engage in hands-on design and characterization of cutting-edge 2T0C neuron circuits, utilizing state-of-the-art tools and techniques. You’ll collaborate with a dynamic, multidisciplinary team of engineers and researchers, tackling exciting challenges related to device performance and energy optimization.
Your work will involve extensive characterization of BEOL FET devices and circuits. You will have the opportunity to propose, specify and design new memory read architectures, that enables the exploration of multi-level synaptic behaviors toward the implementation of more energy and area efficient next-generation neuromorphic systems.
Join us for this unique opportunity to push the boundaries of technology and be part of a transformative journey that could redefine the future of computing! Your contributions could pave the way for breakthroughs in brain-inspired systems, making a lasting impact on the field.
Innovative cooling solutions for 2.5D and 3D electronic systems
As electronic architectures become increasingly complex and dense, managing thermal dissipation is a critical challenge to ensure system reliability and performance. In constrained environments and demanding applications, localized hotspots require innovative cooling solutions compatible with advanced packaging integrations such as 2.5D and 3D. This PhD project is part of this dynamic and aims to explore wafer-level thermal management approaches, relying in particular on advanced 3D integration processes such as direct bonding.
The PhD candidate will contribute to the design and fabrication of test vehicles incorporating temperature sensors and active thermal structures. The main objective will be to assess the efficiency of novel cooling architectures, with a particular focus on integrating microfluidic channels within the stacks, combined with the use of high thermal conductivity materials. The work will include aspects of thermal (and possibly thermo-mechanical) modeling, cleanroom process development, and experimental characterization.
This research topic, at the crossroads of microelectronics and thermal management, offers a stimulating and interdisciplinary framework, closely aligned with emerging industrial needs in advanced packaging.
Vertical GaN power devices development using localized epitaxy
This PhD offers a unique opportunity to enhance your skills in GaN power devices and develop cutting-edge architectures. You’ll work alongside a multidisciplinary team specializing in materials engineering, characterization, device simulation, and electrical measurements. If you’re eager to innovate, expand your knowledge, and tackle state-of-the-art challenges, this position is a valuable asset to your career!
Vertical GaN power components hold great promise for power applications beyond the kV range. Localized epitaxy of GaN enables the creation of thick structures on Si substrates at a competitive cost, with demonstrated success for diodes and pseudo-vertical transistors. However, this approach’s significant surface area limits the energy density of the devices. This PhD aims to develop denser, fully vertical components using layer transfer methods. You’ll study their electrical characteristics to monitor the impact of technological variations on their performance.
Throughout this PhD, you’ll gain comprehensive knowledge in microelectronics processes, electrical characterization, and TCAD (Technology Computer-Aided Design) simulation. You’ll collaborate with a multidisciplinary team including our partner CNRS-LTM and deepen your understanding of GaN power devices, all while being part of a lab dedicated to the development of wide-bandgap power devices. You will have the opportunity to write publications and patents.
Simulation and characterization of integrated structures during and after the millisecond laser annealing step
Laser annealing processes are now used in a large range of applications in most advanced microelectronics technologies. Whether in the context of advanced planar CMOS components or 3D integration technologies, the specific characteristics of laser annealing enables to reach very high temperatures in very short times, at die scale, and to work in conditions out of thermodynamic equilibrium. This has many advantages in terms of physical effects (activation of high dopants with low diffusions, transformation of silicides, etc.), but also thermal budget (high temperatures which remain on the surface of the material). However, this kind of ultrashort optical annealing can generate pattern effect temperature variations on the chip surface between two zones with different radiative andor thermal properties. These temperature differences may alter the electrical performances of the devices and thus have to be evaluated and overcome. A part of this work will consist, by the help of bibliography study, in finding integrative solutions (design, absorbent layer,…), in order to encounter this issue. Besides, at LETI, a wide knowledge of Nanosecond Laser Annealing (NLA) is in place for many years, and process teams are in the acquisition phase of a millisecond laser equipment (DSA). This work will represent, thanks to the numerical simulation, one of the essential building blocks for the development of the millisecond laser annealing at LETI which is mandatory for advanced technologies roadmap.
This interdisciplinary research will encompass fields such as numerical simulations, materials science, microelectronic manufacturing processes. You will benefit from the support of laboratories specializing in integration processes, as well as TCAD simulation environments.