Towards a low-resistive base contact for the InP-HBT transistor
Join CEA LETI for an exciting technological journey! Immerse yourself in the world of III V
based transistors integrated on compatible CMOS circuits for 6 G future communications
This thesis offers the chance to work on a ambitious project, with potential to continue into
a thesis If you're curious, innovative, and eager for a challenge, this opportunity is perfect
for you!
As the consumption of digital content continues to grow, we can foresee that 6 G
communication systems will have to find more capacity to support the increase in traffic
New Sub THz frequencies based systems are a huge opportunity to increase data rate but
are very challenging to build and maturate the power amplifier required to transmit a
signal will have to offer sufficient power and energy efficiency which is not obtained with
actual silicon technology InP based HBTs (Heterojunction Bipolar Transistors) developed
on large Silicon substrates have the potential to meet the requirements and be integrated
as close as possible to the CMOS circuits to enable minimal system/interconnect losses
Sb based semiconductors for GaAsSb HBT are emerging as highly promising materials,
especially for its electrical properties to integrate the Base layer of the Transistor It is
therefore necessary to produce high performance electrical contacts on this type of
semiconductor while remaining compatible with the manufacturing processes of the Si Fab
technology platforms
Throughout
this thesis, you will gain a broad spectrum of knowledge, beneficiate from the
rich technical environment of the 300 200 mm clean room and the nano characterization
platform You will collaborate with multidisciplinary teams to develop a deep understanding
of the ohmic contacts and analyse existing measurements Several apsects of the metal
(Ni or Ti p GaAs 1 x Sb x contact will be investigated
•Identify wet and plasma solutions allowing the GaAsSb native oxide removing without
damaging the surface with XPS and AFM
•Characterize GaAs 1 x Sb x epitaxy doping level (Hall effect, SIMS, TEM)
•Understand the phase sequence during annealing between the semiconductor and the
metal with XRD and Tof SIMS Manage this intermetallic alloys formation to not
deteriorate the contact interface (TEM image associated)
•Evaluate electrical contact properties using TLM structures Measurement of the
specific contact resistivity, sheet resistance of the semiconductor ant transfer length
associated The student will be a motive force to perform electrical tests on an automatic prober
Bayesian Neural Networks with Ferroelectric Memory Field-Effect Transistors (FeMFETs)
Artificial Intelligence (AI) increasingly powers safety-critical systems that demand robust, energy-efficient computation, often in environments marked by data scarcity and uncertainty. However, conventional AI approaches struggle to quantify confidence in their predictions, making them prone to unreliable or unsafe decisions.
This thesis contributes to the emerging field of Bayesian electronics, which exploits the intrinsic randomness of novel nanodevices to perform on-device Bayesian computation. By directly encoding probability distributions at the hardware level, these devices naturally enable uncertainty estimation while reducing computational overhead compared to traditional deterministic architectures.
Previous studies have demonstrated the promise of memristors for Bayesian inference. However, their limited endurance and high programming energy pose significant obstacles for on-chip learning applications.
This thesis proposes the use of ferroelectric memory field-effect transistors (FeMFETs)—which offer nondestructive readout and high endurance—as a promising alternative for implementing Bayesian neural networks.
Field Effect Transistor with Oxide Semiconductor Channel: Multi-Level Synaptic Functions and Analog Neurons
This thrilling PhD position invites you to dive into the groundbreaking field of 2T0C (Two-Transistor, Zero-Capacitor) BEOL FET (Back-End-of-Line Field-Effect Transistor) based neurons and synapses, a revolutionary approach poised to transform neuromorphic computing. As a PhD student, you will be at the forefront of research that bridges advanced semiconductor technology with brain-inspired architectures, exploring how these innovative neuron circuits can emulate synaptic functions and enhance data processing efficiency.
Throughout this project, you will engage in hands-on design and characterization of cutting-edge 2T0C neuron circuits, utilizing state-of-the-art tools and techniques. You’ll collaborate with a dynamic, multidisciplinary team of engineers and researchers, tackling exciting challenges related to device performance and energy optimization.
Your work will involve extensive characterization of BEOL FET devices and circuits. You will have the opportunity to propose, specify and design new memory read architectures, that enables the exploration of multi-level synaptic behaviors toward the implementation of more energy and area efficient next-generation neuromorphic systems.
Join us for this unique opportunity to push the boundaries of technology and be part of a transformative journey that could redefine the future of computing! Your contributions could pave the way for breakthroughs in brain-inspired systems, making a lasting impact on the field.
Innovative cooling solutions for 2.5D and 3D electronic systems
As electronic architectures become increasingly complex and dense, managing thermal dissipation is a critical challenge to ensure system reliability and performance. In constrained environments and demanding applications, localized hotspots require innovative cooling solutions compatible with advanced packaging integrations such as 2.5D and 3D. This PhD project is part of this dynamic and aims to explore wafer-level thermal management approaches, relying in particular on advanced 3D integration processes such as direct bonding.
The PhD candidate will contribute to the design and fabrication of test vehicles incorporating temperature sensors and active thermal structures. The main objective will be to assess the efficiency of novel cooling architectures, with a particular focus on integrating microfluidic channels within the stacks, combined with the use of high thermal conductivity materials. The work will include aspects of thermal (and possibly thermo-mechanical) modeling, cleanroom process development, and experimental characterization.
This research topic, at the crossroads of microelectronics and thermal management, offers a stimulating and interdisciplinary framework, closely aligned with emerging industrial needs in advanced packaging.
Vertical GaN power devices development using localized epitaxy
This PhD offers a unique opportunity to enhance your skills in GaN power devices and develop cutting-edge architectures. You’ll work alongside a multidisciplinary team specializing in materials engineering, characterization, device simulation, and electrical measurements. If you’re eager to innovate, expand your knowledge, and tackle state-of-the-art challenges, this position is a valuable asset to your career!
Vertical GaN power components hold great promise for power applications beyond the kV range. Localized epitaxy of GaN enables the creation of thick structures on Si substrates at a competitive cost, with demonstrated success for diodes and pseudo-vertical transistors. However, this approach’s significant surface area limits the energy density of the devices. This PhD aims to develop denser, fully vertical components using layer transfer methods. You’ll study their electrical characteristics to monitor the impact of technological variations on their performance.
Throughout this PhD, you’ll gain comprehensive knowledge in microelectronics processes, electrical characterization, and TCAD (Technology Computer-Aided Design) simulation. You’ll collaborate with a multidisciplinary team including our partner CNRS-LTM and deepen your understanding of GaN power devices, all while being part of a lab dedicated to the development of wide-bandgap power devices. You will have the opportunity to write publications and patents.
Simulation and characterization of integrated structures during and after the millisecond laser annealing step
Laser annealing processes are now used in a large range of applications in most advanced microelectronics technologies. Whether in the context of advanced planar CMOS components or 3D integration technologies, the specific characteristics of laser annealing enables to reach very high temperatures in very short times, at die scale, and to work in conditions out of thermodynamic equilibrium. This has many advantages in terms of physical effects (activation of high dopants with low diffusions, transformation of silicides, etc.), but also thermal budget (high temperatures which remain on the surface of the material). However, this kind of ultrashort optical annealing can generate pattern effect temperature variations on the chip surface between two zones with different radiative andor thermal properties. These temperature differences may alter the electrical performances of the devices and thus have to be evaluated and overcome. A part of this work will consist, by the help of bibliography study, in finding integrative solutions (design, absorbent layer,…), in order to encounter this issue. Besides, at LETI, a wide knowledge of Nanosecond Laser Annealing (NLA) is in place for many years, and process teams are in the acquisition phase of a millisecond laser equipment (DSA). This work will represent, thanks to the numerical simulation, one of the essential building blocks for the development of the millisecond laser annealing at LETI which is mandatory for advanced technologies roadmap.
This interdisciplinary research will encompass fields such as numerical simulations, materials science, microelectronic manufacturing processes. You will benefit from the support of laboratories specializing in integration processes, as well as TCAD simulation environments.
Selective epitaxial Regrowth for extended Base contact in High-Performance Antimonide-based HBT Transistors
With the rapid expansion of wireless networks and the imminent arrival of 6G, the need for highly efficient communication systems has never been more critical. In this context, frequencies beyond 140 GHz emerge as a key frontier, where cutting-edge technologies leverage advanced semiconductors like InP, delivering unmatched performance beyond what SiGe solutions can achieve. However, III-V components remain expensive, manufactured on small substrates (100 mm for InP), and incompatible with silicon production lines, which ensure higher industrial yields.
In this context, CEA-LETI, in collaboration with CNRS-LTM, is developing a new HBT transistor technology in which the base layer is made of antimonides, having already demonstrated frequency performance beyond the THz range. To enable integration with Si-CMOS fabrication processes, a novel approach for ohmic contact formation is required. This involves selective epitaxial regrowth of a suitable semiconductor material on the base layer of the HBT-GaAsSb transistor.
The PhD candidate will be responsible for identifying the optimal material that meets the required criteria, based on experiments conducted with the epitaxy team, advanced physical characterizations (ToF-SIMS, HR-TEM, EDX), and band structure modeling of the formed heterojunctions. This research will also be complemented by the fabrication of technological test structures to extract the key electrical parameters necessary for optimizing the DC and RF performance of the HBT transistor.
Towards eco innovative, sustainable and reliable piezoelectric technology
Are you looking for a Phd position at the intersection of eco-innovation and high-tech? This subject is for you!
You will participate in efforts aimed at reducing the environmental footprint of piezoelectric (PZE) technology applied to micro actuators and sensors, while maintaining optimal levels of electrical performance and reliability. Currently PZE technology primarily relies on PZT material (Pb(Zr,Ti)O3) which contains lead, as well as electrodes made from materials such as Pt, Ru, and Au, along with doping elements like La, Mn and Nb to enhance piezoelectric properties and electrical performance. These materials not only come with a significant ecological cost but are also facing proven or imminent shortages. In the context of the necessary frugality associated with the energy transition, this PhD position aims to explore more environmentally friendly and sustainable microsystem technologies. The research will create a comparative analysis assessing the ecological footprint, electromechanical performance, and reliability of existing technologies (with lead) versus those under development (lead free). To achieve these objectives, you will employ Life Cycle Analyses (LCA), electromechanical measurements, and reliability tests (accelerated aging tests).
This interdisciplinary research will encompass fields such as eco design materials science, and microelectronic manufacturing processes You will benefit from the support of laboratories specializing in microsystems manufacturing and integration processes, as well as electrical characterization and reliability Collaboration with the “eco innovation” unit at CEA Leti will also enhance the resources available for this project.
Increasing the electrothermal robustness of new SiC devices
Silicon Carbide (SiC) is a semiconductor with superior intrinsic properties than Silicon for high temperature and high power electronics applications. SiC devices are expected to be extensively used in the electrification transition and novel energy management applications. To fully exploit the SiC superior properties, the future semiconductor devices will be used under extreme biasing and temperature conditions. These devices must operate safely at higher current densities, higher dV/dt and higher junction temperatures than Si devices does.
The objective of this thesis is to study the SiC devices fabricated at LETI under these extreme operating conditions, and to optimize their design to fully use the theoretical potential of SiC. The thesis work will include several phases that will be strongly coupled:
- Advanced electro-thermal characterisation (50%), by proposing new approaches to testing components in a box or on a suitable support, using artificial intelligence (AI) tools for data extraction and processing. The work will include adapting standard measurement methodologies to the specific switching characteristics of SiC.
- An assessment (15%) of the design and technological parameters responsible for the operating limits of the components.
- A physico-chemical characterisation component (15%) to analyse failures under these extreme conditions.
- The inclusion of predictive models (20%) for the sensitivity of architectures to extreme conditions and faults, based on modelling.
Study of 3D pattern etch mechanisms into inorganic layers for optoelectronic applications
Optoelectronic devices such as CMOS Image Sensors (CIS) require the realization of 3D structures, convex microlenses, in order to focus photons towards the photodiodes defining the pixels. These optical elements are mandatory for the device efficiency. Their shape and dimension are critical for device performances. In the same way, devices based on diffractive optic and hyperspectral sensors are looking for complex multi-height structures. Finally, recent micro-display technologies for augmented reality (AR) and virtual reality (VR) require 3D structures difficult to achieve with conventional micro-fabrication technics.
Leti is at the state of the art on an alternative photolithography technics, so-called Grayscale. This process can produce a whole range of 3D structures not available with standard photolithography, such as concave, elliptic, pyramids and asymmetrical shapes. These structures could be used in a large number of application fields, like photonics and micro-displays (AR/VR). Once these structures achieved in photoresist, it is necessary to transfer them in an adapted functional layer using plasma etching. The etch mechanisms behind the transfer of micrometric 3D patterns into a polymer layer have been recently studied at Leti. To address new application needs, it is interesting to transfer these structures into silicon based inorganic layers because of their optical properties. Furthermore, the 3D pattern dimensions, currently few micrometers, need to be sub-micrometric for the most advanced technologies. In these condition, pattern transfer fidelity of 3D structures is even more challenging and it underlines why the etch mechanisms need to be well understood.
Currently the transfer into inorganic layers by plasma etching of submicronic 3D patterns obtained with Grayscale photolithography is not well studied in literature. Consequently, this thematic is innovative and has a real benefit. The goal of this PhD thesis is to study and understand the etch mechanisms in order to control the shape and dimension of the transferred structures. The work will be very experimental and will be mainly performed in Leti’s 300mm cleanroom. You will have access to a last generation plasma etch tool and numerous characterization technics. This thesis is in collaboration with the photolithography department and in interaction with different teams, such as the silicon platform and application department.