Advanced fully-depleted Silicon-on-insulator devices for Radio-Frequency applications

The PhD will be performed in the NEXTGEN project aimed at developing the next generation of Silicon-on-insulator devices. Our laboratory is driving the development of the RF active devices: this is a great opportunity to carry out fundamental research using state-of-the art processing equipment and characterization instruments while working in close collaboration with our industrial partners.

you will expected to engage in tasks encompassing:
- perform back-of the-envelope estimation of device properties and assess performace impact of technological choices
- Perform and/or analyze TCAD simulations to gain insight in the RF device behaviour
- data-mining on engineering measurements: grasp the relevant information and identify trends or correlations
- perform extensive periods of time in the lab to conduct or participate in on-wafer RF characterization champaign.
Based on you profile or expectations, above tasks may be dynamically rebalanced during the thesis.

Development and characterization of low temperature Cu-dielectric hybrid bonding

Cu-dielectric hybrid bonding is a technology that enables the assembly of components with very fine interconnection pitch, opening the path to new integrations for advanced applications such as High Performance Computing, Smart Imagers,… Leti has been engaged for more than 10 years in the development of this technology, in partnership with various industries and academies, to master smaller and smaller connection pitches (< 1µm), or to evaluate new techniques such as ‘die-to-wafer’ self-assembly. In this context, low temperature hybrid bonding would allow new integration routes notably for heterogeneous systems (III-V on CMOS,…) or for thermally sensitive components (colored resins, non-volatile memories,…).

The objective of this thesis is to develop and characterize Cu-dielectric hybrid assemblies performed at low temperature, from ambient to 250°C. A first part of the thesis will aim at identifying the dielectric materials that are relevant for the hybrid bonding technology (SiN, SiON, SiCN, …). The critical properties of these materials (permittivity, hygroscopy,…) will be measured and compared to the reference high temperature SiO2. In a second part, the selected dielectrics will be integrated in the ‘wafer-to-wafer’ hybrid bonding technology and each process step (damascene level, surface preparation, direct bonding) will be adapted as needed. The third part of the thesis will be dedicated to the electrical characterization and reliability tests of the obtained low temperature hybrid bonding.

Design and construction of a snubber circuits associated with a power transistors in order to reduce disturbances during fast switching.

The thesis topic is aligned with the European Common Interest Project IPCEI ME/CT, which aims to enhance the value of the European semiconductor sector. It particularly investigates protection systems for direct current (DC) electrical networks against power overloads, short circuits, and electric arc incidents. These complex systems rely on power transistors to manage controlled disconnection of the electrical network, incorporating either separate functions or combined functions with a DC-DC converter.

Despite the abundant literature on the subject, it showcases a variety of approaches and configurations depending on the DC voltage and power levels involved. This project focuses on the activation of DC lines under severe conditions, initially at 400V (low-voltage DC, LVDC) and subsequently at 800V (medium-voltage DC, MVDC).

In the LVDC context, the emergence of GaN HEMT transistors (Gallium Nitride, with a breakdown voltage greater than 650V) has enabled the study of how well these components perform in line disconnection tasks. The rapid switching of the transistor necessitates precise control of the switching trajectory to ensure that the transistor operates within the safety limits specified by the manufacturer. Typically, this involves a snubber circuit for switching assistance. If an overvoltage cannot be avoided, a clamping device is added in parallel to the transistor. Experimental validation of such setups is quite challenging, especially when transistors are used in series or parallel, which motivates the development of alternatives that do not rely on a snubber circuit. However, due to the relative fragility of GaN transistors, this approach is not optimal.

Therefore, the project looks at integrating a switching assistance solution within the GaN transistor package. The production of the transistors and snubbers will utilize the facilities and techniques of the CEA-Leti cleanrooms, with microelectronic manufacturing processes optimized to allow their integration with silicon trench capacities, enabling co-integration with GaN transistors. The components will be assembled after being encapsulated.

Switching tests will initially be conducted within an inverter arm to assess various snubber circuit designs, switching frequencies, speeds, and temperatures. An ultra-fast metrological approach will be developed alongside the transistor design to enable measurements without compromising functionality.

In a later phase, the most promising solutions will also be validated within a back-to-back setup, in the particularly challenging case of opening an inductive DC line.

Study of innovative MOS gate stack for energy efficient SiC power transistors.

Silicon carbide (SiC) components represent the future of power electronics, surpassing silicon technologies in terms of temperature tolerance and power handling capability. At the heart of this evolution, CEA Leti plays a key role in the development of these new generation components, essential for applications such as electric vehicles, charging systems or photovoltaic installations. Our teams provide support to major manufacturers European countries by establishing pilot production lines for GaN and SiC components, as well as by developing SiC substrates with our industrial partners
This thesis aims to develop innovative technological approaches for the design of SiC MOS transistor gates and to evaluate their environmental impact to inform our technological choices. You will deepen the understanding of the physics of SiC MOSFETs by examining different gate architectures. and in
identifying the physical processes that restrict electron mobility in a SiC MOS channel. Questions such as the influence of stress on mobility and the possibility of separating carrier mobility from threshold voltage will be at the heart of your research.

The impact of intrinsic and of extrinsic defects on the dynamic Ron and off-state leakage current of lateral GaN power devices

The intentional doping of lateral GaN power high electron mobility transistors (HEMTs) with carbon (C) impurities is a common technique to reduce buffer conductivity and increase breakdown voltage. However, this comes at the cost of increased intrinsic defects together with degraded dynamic on-resistance (Ron) and current-collapse effects.
The aim of this project is compare the performance of HEMTs devices containing different quantities of extrinsic defects (such as C atoms) and intrinsic defects (such as dislocations), as a function of growths conditions to guide toward optimized buffer structure with good dynamic Ron and low vertical leakage simultaneously.

Ultrasensitive static/dynamic flexible force transducer

In this thesis, the principles and challenges in the development by printing and characterisation of conformable organic piezoelectric matrices for medical use under stress will be examined. A stretchable/conformable piezoelectric sensor, produced on a stretchable substrate, will be developed with materials (PVDF-TrFE type polymer or composite). These developments will make it possible to study the feasibility of using such piezoelectric components in various fields.
The aim of the study carried out to date has been to produce a flexible piezoelectric device based on the principle of a double-sided sensor so as to eliminate the contribution of bending. This sensor must also be stiff enough to be deployed through a 3mm diameter catheter. In this context, the work carried out in this thesis will focus on the development of a flexible piezoelectric sensor capable of converting the mechanical energy of low stresses, coupled with a piezoresistive sensor capable of measuring static stresses. The use of polymers offers greater flexibility, and they are implemented in the form of thin films, making them lightweight and space-saving. In order to achieve these objectives, a dedicated sensor structure guaranteeing redundant measurement (piezoelectric and piezoresistive sensor) will be studied, produced and characterised. The sensor manufacturing process will have to be optimised to increase their efficiency. Optimisation of the architecture of the electrodes and the geometry of the active layers will be tested on a test bench in order to assess their ability to measure static and dynamic stresses simultaneously over the widest possible range of forces. At the same time, fundamental characterisations of the material will be carried out in order to establish correlations between the structure and electrical properties of the sensors.

Design of FD-SOI-specific True Random Number Generator

TRNGs are the essential block of any cryptographic system. Current standards, such as AIS-31, require a stochastic model, which directly relates the model of the physical source of randomness to the entropy of the generated random bits. TRNGs are benchmarked based on their throughput, efficiency and robustness. As such, FD-SOI (Fully Depleted Silicon on Insulator) is a technology well known for its advantages in terms of consumption, but also for the adaptability of its characteristics granted by its unique back bias control acting as a second gate.
This PhD position aims to extend the use of this back gate by studying the opportunities offered by an integrated management of the back gate. By applying a voltage, the BOX allows the adjustment of characteristics at a transistor level. This technique called back biasing, enables the fine-tuning of characteristics and has thus far not been used in the design of security primitives. This technique will be implemented for a FD-SOI specific TRNG based on coherent sampling. Though the novelty and the relevance of the FD-SOI based approach is clear, and motivations to go toward coherent sampling architectures for TRNG have been documented in the literature, the objective of the PhD student will be to bring experimental demonstration, with the support of simulation and modelling of these specific architectures. This will be made possible by a first version of ASIC samples already available at the start of the PhD and the design (by the PhD student) of another ASIC.

Lithography process and design rules co-optimisation for advance microelectronics

Historically, the development of integrated circuit performance has been based on the reduction in size of individual components. The main driving force behind this miniaturization is photolithography, a key step in the semiconductor component manufacturing process. This process consists in reproducing the design of the circuits to be produced in a photosensitive resin. These complex patterns are generated in a single exposure. Light from an ultra-low-wavelength light source (DeepUV) projects a mask image onto the resin. The higher the optical resolution, the greater the miniaturization of the circuits.

When developing new technologies in microelectronics (e.g. FDSOI 10nm, advanced photonics), it is necessary to establish circuit design rules and in parallel to develop photolithography processes to reproduce these designs on the chip. The aim of this thesis is to build bridges between these 2 distinct but closely interwoven worlds, in order to co-optimize their development.

Starting from a practical case for advanced technologies, the thesis work will address the following areas/problems:
- Improving the accuracy and cycle time of the digital lithography models calibration needed to correct optical proximity effects (OPC);
- Using CD-SEM characterizations, identifying borderline design configurations and adjusting design rule constraints accordingly;
- Designing innovative patterns that optimize the dimensional space covered, and evaluating them with a rigorous lithography simulation tool and/or experimentally;
- Integrating lithography results into design tools to establish causal links with device electrical performance.

The thesis will be carried out in Grenoble, at CEA-Leti, internationally recognized for the excellence of its research in the field of microelectronics, and will benefit from the exceptional facilities of the institute's clean room. In particular, the student will be attached to the Laboratoire de PAtterning Computationnel (LPAC), which is exploring ways of improving lithography and etching processes by relying heavily on digital tools, in close partnership with a number of major industrial players. The lab brings together around fifteen people from a wide range of complementary backgrounds (Masters students, student engineers, PhD students, technicians, engineers and researchers, on fixed-term or permanent contracts), who are used to working closely together to give everyone the chance to fulfil their potential and contribute collectively to the progress of the laboratory's work.
The student will be expected to publish and share his/her work at various international conferences.

Could convolutional neural network bring benefits in nanometrics etch processing?

The development and production of energy-efficient electronic components is a major challenge for the microelectronics sector. To answer such a challenge, CEA-Leti and CNRS-LTM does not only focus on building, making and testing new architecture. We also focus on developing greener process and investigating novative solutions to reduce the environmental impact.
Precedent works on process step simulation, based on numerical approach, have already been done in CNRS-LTM institute using HPEM tools specialized on plasma etching or at CEA-LETI considering electronic microscope image processing. To be fully operational, these works still need experimental proof. Process characterization could also be another blocking point, whereas the lateral top view dimension could easily be acquire, for example using CDSEM (10 images/mn), the depth and geometry etch profile need complex and time consuming characterization such as TEM (1 image/d). By combining numerical simulation results, physical characterization and fast CDSEM image acquisition technics the PhD student would be able to train a convolutional neural network in order to predict etch profile geometry. These predictions will be helpfully in the future process development and will bring benefits in terms of time to success and financial/environmental cost reduction.

Realization of MOSFET gates at the sub-10nm node on FD-SOI

As part of the NextGen project and the European ChipACT to ensure the sovereignty and competitiveness of France and Europe in terms of electronic nano-components, CEA-LETI is launching the design of new FD-SOI chips. Already present daily in the automotive or connected object areas, 28-18nm FD-SOI transistors are produced in large volumes by microelectronics founders such as STMicroelectronics. This technology is based on an innovative architecture allowing the production of transistors that are faster, more reliable, and less energy-consuming than transistors on massive substrates. The move to the 10nm node will improve the performance of this technology while being compatible with the issues of energy efficiency and the challenges of miniaturization.
The Field-Effect Transistor (FET) at the 10nm node requires a complex silicon/high-k insulator/metal gate stack. The addition of the high-k dielectric enables to reduce the leakage currents of the gate, but its use coupled with the miniaturization of the components induces new difficulties in the electrical behavior of the FET related to the heterogeneity of the materials constituting the gate stack. To try to resolve these difficulties, this doctorate focuses on an assembly including the deposition of extremely thin metal films on high-k and allowing adjustment of the threshold voltage of the transistors. To study these layers and carry out metallic deposits, CEA-LETI is equipped with PVD equipment for multi-cathode co-sputtering on 300mm silicon wafers. It will make it possible to produce complex alloys and metallic layers adjusted in composition with thickness control at the atomic scale.