SCO&FE ALD materials for FeFET transistors
Ferroelectric Field Effect Transistors FeFET is a valuable high-density memory component suitable for 3D DRAM. FeFET concept combines oxide semiconductors SCO as canal material and ferroelectric metal oxides FE as transistor gate [2, 3]. Atomic layer deposition ALD of SCO and FE materials at ultrathin thickness level (<10 nm) and low temperature (10 cm2.Vs); ultrathin (<5nm) and ultra-conformal (aspect ratio 1:10). The PhD student will beneficiate from the rich technical environment of the 300/200mm CEA-LETI clean-room and the nano-characterization platform (physico-chemical, structural and microscopy analysis, electrical measurements).
The developments will focus on the following items:
1-Comparison of SCO layers (IGZO Indium Gallium Zinc Oxide) fabricated using ALD and PVD techniques: implementation of adapted mesurements techniques and test vehicles
2-Intrinsec and electrical characterization of ALD-SCO (IWO, IGZO, InO) and ALD-EF (HZO) layers: stoichiometry, structure, resistivity, mobility….
3-Co-integration of ALD-SCO and ALD-FE layers for vertical and horizontal 3D FeFET structures
[1]10.35848/1347-4065/ac3d0e
[2]https://doi.org/10.1109/TED.2023.3242633
[3]https://doi.org/10.1021/acs.chemmater.3c02223
Direct metal etch mechanisms study for the BEOL of ultimate SOI nodes
The topic fits into the deployment of silicon technologies at the European level (European chips act), led by CEA-Leti. The focus will be on providing advanced technological building blocks for electrical routing (Back End of Line) of logic and analog devices. The development of increasingly high-performance circuits requires interconnections with more aggressive dimensions. The use of traditional routing materials such as copper is therefore being questioned, as is the conventional back-end of line (BEOL) architecture. This thesis topic will address a breakthrough approach, necessary to achieve these ultimate dimensions.
The objective of this PhD is to develop a BEOL technological building block for the advanced SOI (Silicon on Insulator) nodes through a direct metal etching approach. After a preliminary simulation of the electrical properties of interconnections made with different metals, the work will consist in proposing and implementing an innovative integration. In the first phase, the task will be to determine the design of the electrical test structures and establish an integration scheme. In the second phase, the research work will focus on studying the direct etching of the selected metal using sustainable processes while maintaining the performance of both the processes and the final device. The candidate will be able to rely on the eco-innovation team to perform a comparative life cycle analysis (LCA) of this building block.
The PhD contract is for a duration of 3 years and the research work will take place in the clean rooms of CEA-Leti. To successfully carry out this study, the candidate will have access to state-of-the-art equipment and a cutting-edge work environment.
Study of grayscale photoresists and lithography process optimizations for submicron optical applications
Grayscale lithography process has been used for several years to obtain complex tridimensional structures on semiconductors substrates. This process is particularly adapted for optical and opto-electronics applications.
CEA-LETI has developed a strong expertise on I-line (365nm) grayscale lithography, and is now willing to expand its capabilities and explore grayscale process with DUV (248nm and 193nm) lithography. The objective is to be able to obtain complex 3D structures with critical dimensions less than 1µm.
This PhD work will focus on acquiring a better understanding of the chemical and physical phenomena involved in grayscale photoresists, allowing the optimization of lithography processes. This work will also help with the development of etching processes and new optical models for mask designs.
You will join the lithography team of CEA-LETI, and you will exchange as well with other teams working on this topic (etching, optical simulation). You will have access to a wide range of state of the art equipments installed in LETIs cleanrooms, as well as a world class nanocharacterization platform (PFNC).
Sub-10nm CMOS performances assessment by co-optimization of lithography and design
While developing and introducing new technologies (ex. FDSOI 10nm CMOS), design rules (DRM) are the guidelines used to ensure that a chip design can be reliably fabricated. These rules govern the physical dimensions and spacing of various features used by the designer in the chip layout. They translate both device electrical constraints and manufacturing processes constraints. Among them, lithography and patterning processes are critical step in defining the intricate structures and features on a semiconductor wafer. The most efficient design rules can only be obtained from a co-optimization merging design and lithography constraints.
The objective of this research work is to demonstrate that the use of a digital lithography twin can improve the performance of CMOS by co-optimization of design and lithography (DTCO).
Starting from specific use cases for FDSOI 10nm CMOS technologies, and using advanced lithography simulation tools, the candidate would :
- Develop novel characterization methods to assess lithography process capabilities (hotspot prediction).
- Assess design rules with respect to the lithography process capabilities.
- Quantify, though design rules, lithography impact on device performances.
- Identify significant both process and design limitations and propose paths to challenge them.
As PhD student of CEA-Leti, you will join a technology research institute dedicated to micro and nanotechnologies, within a dynamic and international research environment. You will join the Computational Patterning Laboratory with strong connections with integrated circuit design experts of CEA-Leti. You will benefit from the exceptional facilities of the institute's 300mm clean room and from state-of-the art lithography software tools.
You will be encouraged to publish your work and participate to international conferences and workshops.
Water at the hydrophilic direct bonding interface
The microelectronics industry is making increasing use of hydrophilic direct bonding technology to produce innovative substrates and components. CEA LETI's teams have been leaders in this field for over 20 years, offering scientific and technological studies on the subject.
The key role of water at the bonding interface can be newly understood thanks to a characterization technique developed at CEA LETI. The aim of this thesis is to confirm or refute the physico-chemical mechanisms at play at the bonding interface, depending on the surface preparations and materials in contact.
A large part of this work will be carried out on our cleanroom tools. The characterization of surface hydration using this original technique will be complemented by standard characterizations such as adhesion and adherence energy measurements, FTIR-MIR and SIMS analyses, and X-ray reflectivity at ESRF.
MOCVD growth of 2D ferroelectric In2Se3 films for high density, low consumption nonvolatile memories
Room temperature ferroelectric thin films are the key element of high density, low consumption nonvolatile memories. However, with the further miniaturization of the electronics devices beyond the Moore’s law, conventional ferroelectrics suffer great challenge arising from the critical thickness effect, where the ferroelectricity is unstable if the film thickness is reduced to nanometer or single atomic layer limit. Two-dimensional (2D) materials, thanks to their stable layered structure, saturate interfacial chemistry, weak interlayer couplings, and the benefit of preparing stable ultra-thin film at 2D limit, are promising for exploring 2D ferroelectricity and related device applications. So far, proof of concept demonstrating 2D ferroelectricity has predominantly utilized small flakes (less than a few hundred µm) mechanically exfoliated from a bulk crystal. In particular, atomically thin alpha (or gamma)-In2Se3 lamellar semiconductor preserves a ferroelectric character at 2D limit.
Given the imperative for wafer-scale electronics applications, there is a pressing need for large area growth of high quality 2D materials using bottom-up processes. The objective of this PhD project is to develop the growth of lamellar In2Se3 in its alpha or gamma phase crystal structures by chemical vapor phase epitaxy (MOCVD) on large silicon substrates (200 mm). The proof of concept of a ferroelectric memory cell will be performed by directly depositing a metal electrode on the surface of the 2D ferroelectric material without damaging it.
TeraHertz Landau emission in HgTe/CdTe topological quantum wells
Quantum well heterostructures of HgTe/CdTe are known as topological insulators. They inherit very peculiar electronic properties. One of them is the ability of producing TeraHertz emission from inter-Landau energy level optical transitions. These transitions can be envisioned to lead to coherent optical sources in spectral range where they are basically absent. The PhD Thesis consists in elaborating and characterizing HgTe/CdTe multiple quantum well structures by epitaxy, process them in order to add functionality through optical cavities metallic report or deposition and electrical gating, and finally carry out full range optical spectroscopy of Landau emission in magnetic fields. The PhD will be carried out in a collaborative environment between CEA-Leti and Institut Néel (CNRS) in Grenoble, France, two leading laboratories in the expertise in material growth and Physics of HgTe/CdTe topological insulator systems. The results will help to understand the potential of application of this peculiar material system in TeraHertz laser sources and hopefully lead to the first demonstration of spontaneous emission in the TeraHerz range.
Plasma Etching development for the advanced nodes using SADP techniques
The miniaturization of the electronics components involves the development of new processes. Indeed, the 193nm immersion lithography alone does not permit anymore to achieve the dimensional requirements of the most advanced technological nodes (=10nm). Since the last 10 years, multi-patterning techniques have been developed to overcome the i193nm lithography limitations. Herein, we will study the « Self-Aligned Double Patterning » (SADP) technique that divides by two the initial pitch of the lithographical patterns. This technology relies on a conformal deposition of a dielectric film (spacer) over the initial patterns (mandrel). The spacers will be then used as a mask during the pattern transfer by plasma etching. The small targeted dimensions require a perfect control of the etching processes. However, the etching steps can damage the materials used herein leading to a dimension loss. One of the main challenge will be to control the etching steps and so the plasma-induced modification in order to satisfy the specifications (dimension, profile, material consumption, etch rate, uniformity…). Besides, the goal will be also to propose new SADP approaches allowing us to generate different type of patterns in order to produce planar FDSOI transistors, which is currently little reported in literature.
The challenges of this PhD ?
To develop innovative etching processes
To explore new couple of material (spacer/mandrel) and to propose an industrial integration flow that will be validated by electrical tests
To identify the technological obstacles and to propose solutions for overcoming them
To put in place a reliable characterization protocol in order to detect the physical and chemical modifications of the materials used and to accurately measure the final patterns’ dimensions
Impact of plasma activation on reliability of Cu/SiO2 hybrid bonding integrations
In recent years, CEA-LETI emerged as a leading force in the development of advanced microelectronic manufacturing processes. A key focus has been on wafer-to-wafer Cu/SiO2 hybrid bonding (HB) process, an emerging technology increasingly employed for producing compact, high performance and multifunctional devices. Before bonding, a crucial surface activation step is necessary to enhance the mechanical strength of the assembled structures. Different approaches have been developed, and the most used in the industry is N2-plasma activation. However, this process remains controversial due to undesirable effects, the formation of Cu nodules at the bonding interface between particularly electrical pads and the passivation of Cu pads with chemical complexes. These issues can significantly compromise the electric properties and reliability of devices. In collaboration with STMicroelectronics and IM2NP, this PhD aims at studying the impact of plasma activation on Cu/SiO2 HB integrations.
Self Forming Barrier Materials for Advanced BEOL Interconnects
Context : As semiconductor technology scales down to 10 nm and below, Back End of Line (BEOL) scaling presents challenges, particularly in maintaining the integrity of copper interconnects, where line/via resistance and copper fill are key issues. Copper (Cu) interconnections must resist diffusion and delamination while maintaining optimal conductivity. In the traditional Cu damascene process, metal barriers and a Cu seed layer are deposited by PVD to enable electrochemical copper deposition. As dimensions shrink, it becomes increasingly difficult to incorporate tantalum-based diffusion barriers, even with techniques like atomic layer deposition (ALD), as the barrier thickness must be reduced to just a few nanometers. To address this challenge, a self-forming barrier (SFB) process has been proposed. This process uses copper alloys containing elements such as Mn, Ti, Al, and Mg, which segregate at the Cu-dielectric interface, forming an ultra-thin barrier while also serving as a seed layer for electroplating.
Thesis Project: The PhD candidate will join a leading research team to explore and optimize materials for SFBs using Cu alloys. Focus areas include:
- Material Selection & Characterization: develop and analyze Cu alloy thin films by electrochemical and PVD methods to study their microstructure and morphology.
- Barrier Formation: Control alloy migration at the Cu/dielectric interface during thermal annealing and assess barrier effectiveness.
- Electrical & Mechanical Properties: Evaluate SFB impact on electrical resistance, electromigration, and delamination, especially in accelerated tests.
Required skills : Master's degree in electrochemistry or materials science with a strong interest in applied research. A pronounced interest in experimental work, skills in thin film deposition, electrochemistry and materials characterization (AFM, SEM, XPS, XRD, SIMS). You should be able to conduct bibliographic research and organize your work efficiently.
Work Environment: The candidate will work in a renowned laboratory with state-of-the-art 200/300 mm facilities and will participate in the CEA’s NextGen Project on advanced interconnects for high reliability applications.