Energy-minimizing associative neural networks using resistive memories
This PhD project aims to develop Hopfield-type associative neural networks that perform inference through energy-minimizing dynamics.
The goal is to exploit these dynamics for image denoising and reconstruction close to the sensor, under strict energy and latency constraints.
The network synapses will be implemented in ReRAM crossbar arrays, enabling analog in-memory matrix-vector operations.
The work will focus on architecture dimensioning while accounting for array size, weight quantization, device variability and endurance limits.
Reference models will be developed in PyTorch to evaluate alternative neural dynamics and hardware mapping strategies.
Patch-wise image denoising will serve as the main use case to quantify trade-offs between reconstruction quality, latency and energy consumption.
Particular attention will be paid to the robustness of the networks against hardware non-idealities such as noise, variability and memory drift.
The project will also investigate local on-chip learning mechanisms, allowing slow adaptation to changes in the sensor, scene or memory devices.
These learning rules must remain compatible with the endurance constraints of resistive memories.
Ultimately, the PhD should provide hardware-sizing guidelines and support the design of an experimental test vehicle.
The broader scientific objective is to demonstrate that dynamic associative inference can become an efficient, robust and low-power building block for edge AI.
Junction defect characterization of low therMal Budget SOI MoSFET
Join CEA-Leti and CROMA to analyze in depth junctions of a new technology. Indeed, our transistors are fabricated under restricted thermal budget for 3D sequential integration, making dopants activation very challenging! Our team will support you technically and scientifically to conduct this work. Some data are already available and waiting for your analysis.
During this PhD, you will have the opportunity to perform all theses steps:
From the idea (simulation, bibliography, TCAD) 20%
Processes understanding (implantation, SPER) 10%
Integration & cleanroom fabrication management 10%
Characterization (physical & electrical: noise, DLTS…) 50%
Valorization (presentations, article) 10%
This PhD offers a unique chance to be at the forefront of technological innovation and to make a significant impact in the field of advanced SOI. Join us and take the first step towards an exciting career in research and development!
With a background in microelectronics or nanotechnologies, you are curious about integration of new processes, not afraid about equations and liked semiconductors classes at school. You want to solve complex puzzles and enjoy collaborating with others to figure out innovative solutions.
Sofware support for computing accelerators and memory transferts accelerators
For energy reasons, future computers will have to use accelerators for both computation and memory access (GPUs, TPUs, NPUs, smart DMAs). AI applications have intensive computational requirements in terms of both computing power and memory throughput.
These accelerators are not based on a simple instruction set (ISA), they break the Von Neuman model: they require specialized code to be written manually.
Furthermore, it is difficult to compare the use of these accelerators with code using a non-specialized processor, as the initial source codes are very different.
HybroLang is a hardware-close programming language that allows programs to be written using all of a processor's computing capabilities, while also allowing code to be specialized based on data known at runtime.
The HybroGen compiler has already demonstrated its ability to program in-memory computing accelerators, as well as to optimize code on conventional CPUs by performing innovative optimizations.
This thesis proposes to extend the HybroLang language in order to
- facilitate the programming of AI applications by providing support for complex data: stencils, convolution, sparse computing
- enable code generation both on CPUs and with hardware accelerators currently under development at the CEA (sparse computing, in-memory computing, memory access)
- allow to benchmark different computing architectures with the same initial source code
Ideally, a candidate should have knowledge of computer architecture, programming language implementation, code optimization and compilation.
Sustainable development of digital circuits and systems: Taking planetary boundaries into account
Technological developments in the electronics sector are experiencing rapid growth, accompanied by increasing interest in accounting for their environmental impacts. However, current approaches remain largely focused on relative impact reductions (energy efficiency, resource optimization), without ensuring compatibility with planetary boundaries. In this context, the concept of absolute sustainability emerges as an essential framework for guiding future developments of electronic systems.
This PhD thesis addresses several major scientific challenges: how can carrying capacities and sharing principles (core concepts of absolute sustainability) be identified for the electronics sector and consistently translated down to the levels of digital systems and integrated circuits? How can planetary boundaries be concretely integrated into the design of systems and circuits?
The main objective of the thesis is to move from a logic of relative environmental impact reduction toward designs that are compatible with planetary boundaries. It aims to define socio-technical scenarios to identify sharing principles, to conduct the first absolute life cycle assessment of a digital system, and to propose the first design of a circuit based on absolute limits, paving the way for sustainable development in electronics.
3D interconnects for the design and fabrication of quantum processor units
To increase the performance of quantum computers, three-dimensional (3D) integration is now the key! Using technologies such as flip-chip bonding, multi-layer wiring or even through-silicon vias (TSV), 3D integration offers solutions to increase the number of qubits on a processor, reduce signal loss and cross-talk and even improve thermal management. All of these aspects are essential to continue scaling qubits to achieve fault-tolerant quantum computing.
Our team is developing 3D interconnect technologies (e.g. superconducting microbumps and TSV) for the next generation of quantum processors. This thesis will focus on the electrical and radiofrequency characterization of such interconnects and of the quantum devices integrated nearby to gain knowledge on how these 3D technological bricks may impact the quantum properties.
This position will bring you at the boundary between material, technological and physical challenges of quantum systems. You will work with teams from CEA-LETI and CEA-IRIG. As a PhD candidate, you will take part in the design and layout of test vehicles and in their fabrication. You will also lead the low temperature measurements of the fabricated samples, perform the associated analysis and write reports.
Surface technologies for enhanced superconducting Qubits lifetimes
Materials imperfections in superconducting quantum circuits—in particular, two-level-system (TLS) defects—are a major source of decoherence, ultimately limiting the performance of qubits. Thus, identifying the microscopic origin of possible TLS defects in these devices and developing strategies to eliminate them is key to superconducting qubit performance improvement. This project proposes an original approach that combines the passivation of the superconductor’s surface with films deposited by Atomic Layer Deposition (ALD), which inherently have lower densities of TLS defects, and thermal treatments designed to dissolve the initially present native oxides. These passivating layers will be tested on 3D Nb resonators than implemented in 2D resonators and Qubits and tested to measure their coherence time. The project will also perform systematic material studies with complementary characterization techniques in order to correlate improvements in qubit performances with the chemical and crystalline alteration of the surface.
CORTEX: Container Orchestration for Real-Time, Embedded/edge, miXed-critical applications
This PhD proposal will develop a container orchestration scheme for real-time applications, deployed on a continuum of heterogeneous computing resources in the embedded-edge-cloud space, with a specific focus on applications that require real-time guarantees.
Applications, from autonomous vehicles, environment monitoring, or industrial automation, applications traditionally require high predictability with real-time guarantees, but they increasingly ask for more runtime flexibility as well as a minimization of their overall environmental footprint.
For these applications, a novel adaptive runtime strategy is required that can optimize dynamically at runtime the deployment of software payloads on hardware nodes, with a mixed-critical objective that combines real-time guarantees with the minimization of the environmental footprint.
New generation of 3D ferroelectric memories (FeRAM) with fully BEOL-integrated 1T-1C bitcells
Ferroelectric memories of the FeRAM 1T-1C type based on HZO have the potential to replace the last levels of Cache. CEA-Leti is at the state of the art in this field at the 22nm node [1], with 1T-1C bitcells already denser than those of SRAM. In this approach, the selection transistor (1T) is a front-end transistor, and the three-dimensional ferroelectric capacitor (1C) is integrated in the back-end.
It has been shown by Micron [2] that the use of a three-dimensional back-end transistor made of polycrystalline silicon allows 1/ to densify the bitcell, 2/ to stack several levels of FeRAM, and 3/ to use the CMOS under the arrays for control logic (CMOS Under Array - CuA).
The objective of this thesis is to evaluate other types of selectors, in particular vertical amorphous oxide semiconductor field-effect transistors (AOSFETs) integrated in the back-end, for the new generations of FeRAM memories. The characteristics of these back-end transistors [3] (low Ioff, low Ion, low Vth) should offer significant advantages for the operation of FeRAM memory arrays at very low voltages (< 1V) while allowing the integration of very dense 1T-1C bitcells entirely in the back-end.
The thesis will primarily be oriented towards DTCO (Design Technology Co-Optimization) to propose dense bitcells using realistic integration schemes. It will also be able to rely on recent experimental results obtained at CEA, both on AOSFETs and on 3D ferroelectric capacitors [1], with a view to first silicon demonstrations.
[1] S. Martin et al., IEDM 2024; [2] N. Ramaswamy et al., IEDM 2023; [3] S. Deng et al., VLSI 2025
Advanced SOI technologies: Design, Integration & Electrical characterization
Join CEA-Leti to develop a technological module (localized ground plane) for various applications (EU FDSOI, RF devices, ultra-miniaturized pixels, cryo-RF and quantum).
This PhD topic is challenging since you will design step by step a specific module and test it electrically. Our team will support you technically and scientifically to conduct this work. Some data are already available and waiting for your analysis.
During this PhD, you will have the opportunity to learn how a module/device is designed step by steps:
From the idea (simulation, bibliography)
Material & Processes understanding (bonding, CMP)
Integration & cleanroom fabrication management
Characterization (physical & electrical: mobility, interface traps)
Valorization (presentations, article)
Development of multiplexed photon sources for quantum technologies
Quantum information technologies offers several promises in domains such as computation or secured communications. Because of their robustness against decoherence, photonic qubits are particularly interesting for quantum communications applications, even at room temperature. They also offers an alternative to other qubits technologies for quantum computing. For the large-scale deployment of those applications, it is necessary to have cheap, compact and scalable devices. To reach this goal, silicon photonics platform is attractive. It allows implementing key components such as generation, manipulation and detection of photonic qubits. On the silicon platform, the photonic qubits are generated by pair through non linear process. has several benefits, such as working at room temperature, the ability to generate heralded single photon, or undistiguishable photons with spatially distinct sources.
The goal of this thésis is to work on the development, the fabrication monitoring, and the characterization in the laboratory of multiplexed photon sources on silicon chips to overcome the limits in the process of photon generation with one source. In order to achieve a full integration on chip, it is also essential to properly filter unwanted light in order to keep only the photons that are of interest. As a consequence you will also focus on the development of intgrated filters with high rejection rate.