SiGe HBT LNA for cryogenic applications: design, characterization and optimization
The global race to build a quantum computer is heating up! These cutting-edge systems operate at temperatures below 4 K to preserve the delicate quantum states essential for computation. To achieve efficient control and detection, conventional electronic circuits must perform reliably at cryogenic temperatures, in close proximity to the quantum processor, thereby reducing wiring complexity and boosting performance. Beyond quantum computing, other domains—such as space exploration, high-performance computing, or high-energy physics—also require transistors capable of operating below 100 K.
During this phD, you will perform radiofrequency (RF) electrical characterization and modeling of Silicon-Germanium Heterojunction Bipolar Transistors in cryogenic environment, contributing to a deeper understanding of their behavior and optimizing their potential for extreme-condition applications. The objectives are twofold:
1.RF Electrical Characterization and Modeling:
•Conduct RF electrical measurements of SiGe HBTs at cryogenic temperatures.
•Develop accurate models to describe their behavior in cryogenic environments.
2.Optimization of Low-Noise Amplifiers (LNAs):
•Study the low-temperature behavior of individual passive and active devices composing an LNA.
•Optimize the design of low-noise amplifiers (LNAs) for cryogenic applications.
3D interconnects for the design and fabrication of quantum processor units
To increase the performance of quantum computers, three-dimensional (3D) integration is now the key! Using technologies such as flip-chip bonding, multi-layer wiring or even through-silicon vias (TSV), 3D integration offers solutions to increase the number of qubits on a processor, reduce signal loss and cross-talk and even improve thermal management. All of these aspects are essential to continue scaling qubits to achieve fault-tolerant quantum computing.
Our team is developing 3D interconnect technologies (e.g. superconducting microbumps and TSV) for the next generation of quantum processors. This thesis will focus on the electrical and radiofrequency characterization of such interconnects and of the quantum devices integrated nearby to gain knowledge on how these 3D technological bricks may impact the quantum properties.
This position will bring you at the boundary between material, technological and physical challenges of quantum systems. You will work with teams from CEA-LETI and CEA-IRIG. As a PhD candidate, you will take part in the design and layout of test vehicles and in their fabrication. You will also lead the low temperature measurements of the fabricated samples, perform the associated analysis and write reports.
Understanding the origin of charge noise in quantum devices
Thanks to strong collaborations between teams from several research institutes and the cleanroom facilities at CEA-LETI, Grenoble has been a pioneer in the development of spin qubit devices as a platform for quantum computing. The lifetime of these spin qubits is highly sensitive to fluctuations in the qubit's electrical environment, known as charge noise. Charge noise in spin qubit devices potentially originates from trapping/detrapping events within the amorphous and defective materials (e.g., SiO2, Si3N4). This PhD project aims to better understand the origin of this noise through numerical simulations, and guide the development of quantum devices towards lower noise levels and higher quality qubits.
The goal of this PhD position is to improve the understanding of noise in spin qubit devices through multi-scale simulations going from the atomistic to the device level. The PhD candidate will use codes developed at CEA for the numerical modeling of spin qubits and will leverage supercomputing facilities to perform the simulations. Depending on the candidate’s profile and interests, code development may be considered. The work will also involve collaborations with experimentalists to validate simulation methods and to aid in the interpretation of experimental results.
Surface technologies for enhanced superconducting Qubits lifetimes
Materials imperfections in superconducting quantum circuits—in particular, two-level-system (TLS) defects—are a major source of decoherence, ultimately limiting the performance of qubits. Thus, identifying the microscopic origin of possible TLS defects in these devices and developing strategies to eliminate them is key to superconducting qubit performance improvement. This project proposes an original approach that combines the passivation of the superconductor’s surface with films deposited by Atomic Layer Deposition (ALD), which inherently have lower densities of TLS defects, and thermal treatments designed to dissolve the initially present native oxides. These passivating layers will be tested on 3D Nb resonators than implemented in 2D resonators and Qubits and tested to measure their coherence time. The project will also perform systematic material studies with complementary characterization techniques in order to correlate improvements in qubit performances with the chemical and crystalline alteration of the surface.
CORTEX: Container Orchestration for Real-Time, Embedded/edge, miXed-critical applications
This PhD proposal will develop a container orchestration scheme for real-time applications, deployed on a continuum of heterogeneous computing resources in the embedded-edge-cloud space, with a specific focus on applications that require real-time guarantees.
Applications, from autonomous vehicles, environment monitoring, or industrial automation, applications traditionally require high predictability with real-time guarantees, but they increasingly ask for more runtime flexibility as well as a minimization of their overall environmental footprint.
For these applications, a novel adaptive runtime strategy is required that can optimize dynamically at runtime the deployment of software payloads on hardware nodes, with a mixed-critical objective that combines real-time guarantees with the minimization of the environmental footprint.
New generation of 3D ferroelectric memories (FeRAM) with fully BEOL-integrated 1T-1C bitcells
Ferroelectric memories of the FeRAM 1T-1C type based on HZO have the potential to replace the last levels of Cache. CEA-Leti is at the state of the art in this field at the 22nm node [1], with 1T-1C bitcells already denser than those of SRAM. In this approach, the selection transistor (1T) is a front-end transistor, and the three-dimensional ferroelectric capacitor (1C) is integrated in the back-end.
It has been shown by Micron [2] that the use of a three-dimensional back-end transistor made of polycrystalline silicon allows 1/ to densify the bitcell, 2/ to stack several levels of FeRAM, and 3/ to use the CMOS under the arrays for control logic (CMOS Under Array - CuA).
The objective of this thesis is to evaluate other types of selectors, in particular vertical amorphous oxide semiconductor field-effect transistors (AOSFETs) integrated in the back-end, for the new generations of FeRAM memories. The characteristics of these back-end transistors [3] (low Ioff, low Ion, low Vth) should offer significant advantages for the operation of FeRAM memory arrays at very low voltages (< 1V) while allowing the integration of very dense 1T-1C bitcells entirely in the back-end.
The thesis will primarily be oriented towards DTCO (Design Technology Co-Optimization) to propose dense bitcells using realistic integration schemes. It will also be able to rely on recent experimental results obtained at CEA, both on AOSFETs and on 3D ferroelectric capacitors [1], with a view to first silicon demonstrations.
[1] S. Martin et al., IEDM 2024; [2] N. Ramaswamy et al., IEDM 2023; [3] S. Deng et al., VLSI 2025
Advanced SOI technologies: Design, Integration & Electrical characterization
Join CEA-Leti to develop a technological module (localized ground plane) for various applications (EU FDSOI, RF devices, ultra-miniaturized pixels, cryo-RF and quantum).
This PhD topic is challenging since you will design step by step a specific module and test it electrically. Our team will support you technically and scientifically to conduct this work. Some data are already available and waiting for your analysis.
During this PhD, you will have the opportunity to learn how a module/device is designed step by steps:
From the idea (simulation, bibliography)
Material & Processes understanding (bonding, CMP)
Integration & cleanroom fabrication management
Characterization (physical & electrical: mobility, interface traps)
Valorization (presentations, article)
Development of multiplexed photon sources for quantum technologies
Quantum information technologies offers several promises in domains such as computation or secured communications. Because of their robustness against decoherence, photonic qubits are particularly interesting for quantum communications applications, even at room temperature. They also offers an alternative to other qubits technologies for quantum computing. For the large-scale deployment of those applications, it is necessary to have cheap, compact and scalable devices. To reach this goal, silicon photonics platform is attractive. It allows implementing key components such as generation, manipulation and detection of photonic qubits. On the silicon platform, the photonic qubits are generated by pair through non linear process. has several benefits, such as working at room temperature, the ability to generate heralded single photon, or undistiguishable photons with spatially distinct sources.
The goal of this thésis is to work on the development, the fabrication monitoring, and the characterization in the laboratory of multiplexed photon sources on silicon chips to overcome the limits in the process of photon generation with one source. In order to achieve a full integration on chip, it is also essential to properly filter unwanted light in order to keep only the photons that are of interest. As a consequence you will also focus on the development of intgrated filters with high rejection rate.
Injection-Locked Oscillators based Liquid Neural Networks for Generative Edge Intelligence
This PhD aims to design analog liquid neural networks for generative edge intelligence. Current neuromorphic architectures, although more efficient through in-memory computing, remain limited by their extreme parameter density and interconnection complexity, making their hardware implementation costly and difficult to scale. The Liquid Neural Networks (LNN), introduced by MIT at the algorithmic level, represent a breakthrough: continuous-time dynamic neurons capable of adjusting their internal time constants according to the input signal, thereby drastically reducing the number of required parameters.
The goal of this PhD is to translate LNN algorithms into circuit-level implementations, by developing ultra-low power time-mode cells based on oscillators that reproduce liquid dynamics, and interconnecting them into a stable, recurrent architecture to target generative AI tasks. A silicon demonstrator will be designed and validated, paving the way for a new generation of liquid neuromorphic systems for Edge AI.
Superconducting silicide contacts on hyperdoped silicon by nanosecond pulsed-laser annealing
In the race towards building a quantum computer, there is a deep interest in fabricating devices based on the robust and scalable silicon FD-SOI technology. One example is the Josephson Field Effect Transistor (JoFET) whose operability relies on the high transparency of the interface between the superconducting source/drain regions and the semiconducting channel. Such transparency could be improved by doping the source/drain regions, and hence lowering the Schottky barrier height at the superconductor/semiconductor interfaces.
This PhD aims at developing highly transparent superconducting silicide contacts on a 300 mm production line using Nanosecond Pulsed Laser Annealing (NPLA). NPLA will play a key role for reaching extremely high doping concentrations in silicon [1,2], then forming the superconducting silicides (CoSi2, V3Si) with minimal thermal budget and related dopant deactivation. A particular focus will be devoted on the stresses during silicide formation and their impact on the superconducting critical temperature. Also, the distribution of dopants will be assessed by Atom Probe Tomography (APT), an advanced 3D imaging technique capable of imaging the distribution of dopants at the atomic scale [3]. Finally, electrical measurements on fabricated junctions and transistors will be carried out at low temperature (< 1 K) in order to evaluate the transparency of the superconducting contacts.