# Study of the stability of Si-CMOS Structures for the implementation of Spin Qubits

Silicon-based spin qubits in CMOS structures stand out for their compatibility with semiconductor technologies and their scalability potential. However, impurities and defects introduced during fabrication lead to noise and instability, which affect their performance.

The objective is to characterize devices fabricated at CEA-Leti, from room temperature to cryogenic temperatures, to evaluate their quality and understand the physical mechanisms responsible for their instability. The goal is to improve the design of the devices and ideally establish a method to identify the most promising devices without requiring measurements at very low temperatures.

The candidate should have skills in the following areas:

- Experimental physics and semiconductors.

- Algorithm programming and data analysis.

- Knowledge in nanofabrication, low-temperature physics, and quantum physics (desirable).

# Formal verification for quantum programs compilation

While recent progress in quantum hardware open the door for significant speedup in cryptography as well as additional key areas (biology, chemistry, optimization, machine learning, etc), quantum algorithms are still hard to implement right, and the validation of such quantum programs is a challenge.

Adapting the best practice for classical computing formal verification -- deductive verification, first order logic reasoning--, our recent development of Qbricks enables formal specification -- circuit well-formedness, functional behavior, complexity --and verification for quantum programming with ideal qubits.

The goal of PhD position is to extend this practice into the quantum compilation chain by making it usable from mainstream quantum programming environments (high-level programming and imperative paradigm).

Possibilities include, among others, developing (1) a formally verified intermediate representation for fault-tolerant implementations (2) reasoning tools for certifying quantum circuit transformation functions, (3) automatic verification tools over equivalence and/or proximity relations between quantum circuits.

# Brain Computer Interface - Investigating new ways for extracting the information

In 2011, our laboratory developed the ASIC integrated into the WIMAGINE® implant, which played a crucial role in the motor recovery of a patient paralyzed due to a spinal cord injury. We are now focusing on designing a new generation of electronic interfaces to interact with the brain to enhance performance and energy efficiency.

This PhD project will involve designing an innovative information processing chain for capturing and transmitting neural signals within an implantable medical device. The work will encompass the conceptualization of the architecture, integration into an integrated circuit, and system evaluation. This project represents an exceptional opportunity to delve into the fields of sensor electronics, signal processing, and artificial intelligence. The objective is to efficiently transform neural signals into actionable data through a data-driven method.

# Quantum Machine Learning in the era of NISQ: can QML provide an advantage for the learning part of Neural Networks?

Quantum computing is believed to offer a future advantage in a variety of algorithms, including those challenging for traditional computers (e.g., Prime Factorization). However, in an era where Noisy Quantum Computers (QCs) are the norm, practical applications of QC would be centered around optimization approaches and energy efficiency rather than purely algorithmic performance.

In this context, this PhD thesis aims to address the utilization of QC to enhance the learning process of Neural Networks (NN). The learning phase of NN is arguably the most power-hungry aspect with traditional approaches. Leveraging quantum optimization techniques or quantum linear system solving could potentially yield an energy advantage, coupled with the ability to perform the learning phase with a less extensive set of training examples.

# Clip approach for improving energy efficiency of hardware embedding combinations

In a global context of task automation, artificial neural networks are currently used in many domains requiring the processing of data from sensors: vision, sound, vibration.

Depending on different constraints, the information processing can be done on the Cloud (SIRI, AWS, TPU) or in an embedded way (NVidia's Jetson platform, Movidius, CEA-LIST's PNeuro/DNeuro). In this second case, many hardware constraints must be taken into account when dimensioning the algorithm. In order to improve the porting on hardware platforms, LIST has developed innovative state-of-the-art methods allowing to aggressively quantize the parameters of a neural network as well as to modify the coding of the activations to reduce the number of calculations to be performed.

The energy efficiency of neuromorphic architectures with equivalent technology is constrained by the classic paradigm of flexibility vs. efficiency. In other words, the more different tasks (and networks) an architecture is capable of performing, the less energy-efficient it becomes. While this relationship cannot be circumvented for a wide variety of algorithms, neural networks are parametric functions, learned for one and therefore potentially adaptable to other tasks by partial modification of the topology and/or parameters.

One technique, CLIP, seems to provide an answer, with a strong capacity for adaptation to a variety of tasks and the possibility of using multimodality. In its original form, CLIP is presented as a method for matching text and images to create a classification task.

The aim of this thesis is to study the hardware implementation of CLIP by proposing a dedicated architecture. The thesis is organized into 3 main phases, beginning with a study of CLIP's mechanisms, the operations to be performed and the consequences for embedding networks. Secondly, hardware optimizations applicable to CLIP, such as quantization (or others) and an estimation of flexibility vs. applicative generality. Finally, an architectural and implementation proposal to measure energy efficiency.

# Stabilizer-universal graph states for robust quantum networks and quantum error correction

The last years have seen notable advances in quantum technologies, consolidating the development of basic requirements for the deployment of future quantum networks. Such networks are essential to distributed quantum information applications, and may serve various purposes, e.g., enabling the transmission of quantum states between physically distant parties, or improving the computational capabilities of quantum computers by combining multiple quantum processors. When only local operations and classical communication (LOCC) are allowed, the initial quantum state shared between the parties plays a key role, and may both enable specific applications, or provide the means to answer unsettled theoretical questions.

This PhD project aims at exploring k-stabilizer universal quantum states, that is, n-qubit quantum states that allow inducing any stabilizer state on any subset of k qubits, by using LOCC protocols only. Stabilizer states can be described, up to local unitaries, by the formalism of graph states, representing one of the most important classes of multipartite entanglement, and a powerful resource for many multipartite quantum protocols. The goal of the thesis is threefold. A first objective is to develop deterministic methods to construct k-stabilizer universal graph states on a number of qubits n quadratic in k (theoretical bound), thus improving the scalability and efficiency with respect to current state of the art. A second objective is to investigate the robustness of the derived protocol, for preparing a desired quantum stabilizer state on a subset of k qubits, to potential threats posed by malicious parties or qubit losses. Finally, the last objective of the thesis is to identify connections and implications between k-stabilizer universal graph states, robustness, and quantum error correction, as a way to devise new constructions of quantum error correcting codes of independent interest, or to increase the reliability of quantum networks.

# Development of integrated superconducting nanowire single photon detectors on silicon for photonic quantum computing

The development of quantum technologies represents a major challenge for the future of our society, in particular to build unhackable communications as well as quantum computers offering computing power well beyond that available with current supercomputers. Photonic quantum bits (or qubits), in the form of single photons, are robust against quantum decoherence and are therefore very attractive for these applications. At CEA-LETI, we are developping an integrated quantum photonics technology on silicon wafers, compatible with industrialization, comprising key building blocks for qubit generation, manipulation and detection on-chip.

The PhD project will be focused on the development of integrated superconducting nanowire single photon detectors, sensitive to the presence of a single photon, required for photonic quantum computing. The objective will be the design of superconducting single photon detectors integrated with ultra-low loss waveguides used for the core of the quantum computing processor, the development of a clean room fabrication process compatible with the existing silicon photonics platform and the characterization of the detector figures of merit (detection efficiency, dark count rate, timing performances) using attenuated lasers. The final goal of the PhD will be the integration of small circuits including several detectors on-chip to characterize the purity and indistinguishability of single photons emitted by a quantum dot source developped in parallel at CEA-IRIG (also located in Grenoble).

This PhD work will be carried out in collaboration between CEA-LETI and CEA-IRIG and will be a strategic cornerstone at the heart of future generations of quantum photonic processors featuring several tens of qubits.

# The technology choice in the eco-design of AI architectures

Electronic systems have a significant environmental impact in terms of resource consumption, greenhouse gas emissions and electronic waste, all of which are experiencing a massive upward trend. A large part of the impact is due to production, and more particularly the manufacturing of integrated circuits, which is becoming more and more complex, energy-intensive and resource-intensive with new technological nodes. The technology used for the implementation of a circuit has direct effects on the environmental costs for production and use, the lifespan of the circuit and the possibilities of several life cycles in a circular economy perspective. The technological choice therefore becomes an essential step in the ecodesign phase of a circuit.

The thesis aims to integrate the exploration of different technologies into an eco-design flow of integreted circuit. The purpose of the work is to define a methodology for a systematic integration of the technological choice into the flow, with identification of the best configuration of the architecture implemented for maximizing the lifespan and taking into account the strategies of circular economy. The architectures targeted by the thesis fall into the field of embedded AI, which is experiencing an upward deployment trend and involves major societal challenges. The thesis will constitute a first step in research towards sustainable embedded AI.

# Development and integration of technological boosters for strain engineering in advanced FDSOI channels

Fully Depleted Silicon On Insulator FDSOI CMOS technology has been demonstrated to be highly efficient for low power and low leakage applications such as mobile, internet of things or wearable. This is mainly due to the excellent electrostatic control in the transistor channel, a low variability and high application flexibility (owing to a great back-biasing capability). The work of this thesis will deal with the strain integration in FDSOI technology in order to boost and optimize the CMOS performance. Different strain introduction techniques will be evaluated, in particular the engineering of stress in the channel to enhance the carrier mobility. This strain can come directly from from the channel (SiGe channel for pMOS), from the BOX (through a BOX creep techniques), or through the source/drain.The student, with the support of the whole team, will have in charge the review of most promising solutions, first from a theoretical point of view and then with their development and implementation on morphological and electrical dedicated structures. Extensive mechanical and device simulations will be done to correlate the different results.

# Partitioning of spin Qubits control electronics architecture: co-design of cryoCMOS and room-temperature hardware

Quantum algorithms capable of demonstrating a quantum advantage will require the use of quantum processors (QPU) with several thousands of qubits. The design of such a quantum computer is a multidisciplinary challenge at the heart of quantum engineering. Control electronics face particular constraints related to the cryogenic temperature at which qubits operate. Leveraging its expertise in silicon-based technologies, the CEA aims to integrate thousands of semiconductor qubits within a single QPU.

The primary objective of this thesis is to propose an innovative digital and analog qubit control architecture that scales to thousands of spin qubits, by distributing electronics between different stages of the cryostat and the exterior at ambient temperature. The second objective is to create prototypes of this control chain to demonstrate the feasibility and performance of such an architecture.

The work will build upon an existing architecture at ambient temperature and microelectronic blocks developed at cryogenic temperatures within the CEA. New blocks and corresponding circuits will be developed to reach the targetted scale-out quantum architecture. The circuits will be fabricated, tested and measured, and will be published in scientific publications.