DCDC converter based on chiplet for HPC applications
High-performance computing (HPC) is becoming more and more critical for the AI
advancement. HPC requires significant amount of power for the needed processing
and struggles with thermal dissipation issues. Recent research highlights the need for
innovative solutions to improve power management for AI processors.
In our research team, you will be responsible for developing an enhanced power
management unit to provide a stable power supply for high-performance processors.
By exploring cutting-edge DC-DC converter topologies and emerging silicon passive
components (inductors and capacitors), the main objective is to design a highly efficient
DC-DC converter that optimizes both power efficiency and density. This project also
involves analyzing power distribution networks and integrated circuit design to optimize
the overall power delivery efficiency with relatively small form factor.
As a PhD student, you will be engaged in various technical tasks, from system-level
analysis to IC design. Working in an IC-design lab, you will collaborate with digital
design and component teams to address both device- and system-level challenges.
Your tasks will be distributed across system architecture (40%), passive component
analysis (20%), and converter design (40%).
Superconducting RF Filters for Quantum Applications
Within the Quantum Devices Laboratory, you will work in an environment ranging from fundamental physics to new nano-electronics technologies, with a team that collaborates closely with quantum computing startups and physicists from CEA-IRIG and Institut Néel.
The operating conditions of qubits (cryogenic temperatures <= 1K, GHz frequencies , high signal density) require the development of suitable components and technological bricks. In particular, the passive radiofrequency components developed around the CEA-LETI superconducting interposer technology show extremely interesting electrical properties up to several GHz. These elements, including inductors available over wide value ranges, have already made it possible to establish the first proofs of concept for very compact and low-loss RF filters. The integration of superconducting materials now makes it possible to envisage the creation of new high-performance filters adapted to signal management in cryogenic environments.
You will be required to develop your expertise in the physics of materials and superconducting components. You will study the different superconducting filters that exist in the scientific literature. Using the models developed in the laboratory and the results of the RF measurements in which you will participate, and relying on 3D RF electromagnetic simulation, you will contribute to the design of different RF filters and functions that meet the needs of cryogenic applications.
3D Hybrid Synapses for Energy-Efficient and Adaptive Edge AI
This PhD thesis is part of the growing field of embedded AI for the Internet of Things (IoT), where constraints in energy, area, and connectivity require rethinking the learning mechanisms of neural networks. The goal is to design neuromorphic architectures based on 3D hybrid synapses combining FeRAM and ReRAM, within an in-memory computing framework. The objective is to enable local adaptation of the model—drawing from machine learning approaches and potentially compatible with plasticity mechanisms such as STDP, VDSP, etc.—while maintaining efficient inference adapted to naturally asynchronous information. The PhD student will develop a heterogeneous memory architecture, design an appropriate local learning protocol, and implement integrated circuit demonstrators. Experimental validation on edge-relevant tasks (e.g., sensory classification) will assess power consumption, network accuracy, and adaptability. Publications and patents are expected outcomes of the thesis.
Study of the stability of Si-CMOS Structures for the implementation of Spin Qubits
Silicon-based spin qubits in CMOS structures stand out for their compatibility with semiconductor technologies and their scalability potential. However, impurities and defects introduced during fabrication lead to noise and instability, which affect their performance.
The objective is to characterize devices fabricated at CEA-Leti, from room temperature to cryogenic temperatures, to evaluate their quality and understand the physical mechanisms responsible for their instability. The goal is to improve the design of the devices and ideally establish a method to identify the most promising devices without requiring measurements at very low temperatures.
The candidate should have skills in the following areas:
- Experimental physics and semiconductors.
- Algorithm programming and data analysis.
- Knowledge in nanofabrication, low-temperature physics, and quantum physics (desirable).
Automatization of quantum computing kernel writing for quantum applications
The framework of Hamiltonian simulation opens up a new range of computational approaches for quantum computing. These approaches can be developed across all relevant fields of quantum computing applications, including, among others, partial differential equations (electromagnetism, fluid mechanics, etc.), quantum machine learning, finance, and various methods for solving optimization problems (both heuristic and exact).
The goal of this thesis is to identify a framework where these approaches—based on Hamiltonian simulation or block-encoding techniques—are feasible and can be written in an automated way.
This work could extend to the prototyping of a code generator, which would be tested on practical cases in collaboration with European partners (including a few months of internship within their teams).
Software support for sparse computation
The performance of computers has become limited by data movement in the fields of AI, HPC and embedded computing. Hardware accelerators do exist to handle data movement in an energy-efficient way, but there is no programming language that allows them to be implemented in the code supporting the calculations.
It's up to the programmer to explicitly configure DMAs and use function calls for data transfers and do program analysis to identify memory bottleneck
In addition, compilers were designed in the 80s, when memories worked at the same frequency as computing cores.
The aim of this thesis will be to integrate into a compiler the ability to perform optimizations based on data transfers.
Quantum computing with nuclear spins
Nuclear spins in solids are amongst the quantum systems with the longest coherence times, up to minutes or even hours, and as such are attractive qubit candidates; however, controlling and reading out individual nuclear spins is highly challenging. In our laboratory, we have developed a new way to do so. The nuclear spin qubits are interfaced by an electron spin ancilla to which they are coupled by the hyperfine interaction. The electron spin is then measured by microwave photon counting at millikelvin temperatures [1,2]. Nuclear-spin single-shot readout is performed via the electron spin [3], and coherent control is achieved through the use of microwave Raman transitions [4]. The electron spins are Er3+ ions in a CaWO4 crystal, and the nuclear spins are 183W atoms in the matrix, which have a spin 1/2.
[1] E. Albertinale et al., Nature 600, 434 (2021)
[2] Z. Wang et al., Nature 619, 276 (2023)
[3] J. Travesedo et al., arxiv (2024)
[4] J. O'Sullivan et al., arxiv (2024)
Modelling spin shuttling in Si and Ge spin qubits
Silicon and Germanium spin qubits have made outstanding progress in the past few years. In these devices, the elementary information is stored as a coherent superposition of the spin states of an electron or hole confined in a quantum dot embedded in a Si/SiO2 or SiGe heterostructure. These spins can be manipulated electrically and are entangled through exchange interactions, allowing for a variety of one- and two-qubit gates required for quantum computing and simulation. Grenoble is promoting original spin qubit platforms based on Si and Ge, and holds various records in spin lifetimes and spin-photon interactions. At CEA/IRIG, we support the progress of these quantum technologies with state-of-the-art modelling. We are, in particular, developing the TB_Sim code, able to describe very realistic qubit structures down to the atomic scale if needed.
Spin shuttling has emerged recently as a resource for spin manipulation and transport. A carrier and its spin can indeed be moved (shuttled) coherently between quantum dots, allowing for the transport of quantum information on long ranges and for the coupling between distant spins. The shuttling dynamics is however complex owing to the spin-orbit interactions that couple the motion of the carrier to its spin. This calls for a comprehensive understanding of these interactions and of their effects on the evolution and coherence of the spin. The aim of this PhD is to model shuttling between Si/Ge spin qubits using a combination of analytical and numerical (TB_Sim) techniques. The project will address spin manipulation, transport and entanglement in arrays of spin qubits, as well as the response to noise and disorder (decoherence). The PhD candidate will have the opportunity to interact with a lively community of experimentalists working on spin qubits at CEA and CNRS.
Combined Software and Hardware Approaches for Large Scale Sparse Matrix Acceleration
Computational physics, artificial intelligence and graph analytics are important compute problems which depend on processing sparse matrices of huge dimensions. This PhD thesis focuses on the challenges related to efficiently processing such sparse matrices, by applying a systematic software are hardware approach.
Although the processing of sparse matrices has been studied from a purely software perspective for decades, in recent years many dedicated, and very specific hardware, accelerators for sparse data have been proposed. What is missing is a vision of how to properly exploit these accelerators, as well as standard hardware such as GPUs, to efficiently solve a full problem. Prior to solving a matrix problem, it is common to perform pre-processing of the matrix. This can include techniques to improve the numerical stability, to adjust the form of the matrix, and techniques to divide it into smaller sub-matrices (tiling) which can be distributed to processing cores. In the past, this pre-processing has assumed homogenous compute cores. New approaches are needed, to take advantage of heterogeneous cores which can include dedicated accelerators and GPUs. For example, it may make sense to dispatch the sparsest regions to specialized accelerators and to use GPUs for the denser regions, although this has yet to be shown. The purpose of this PhD thesis is to take a broad overview of the processing of sparse matrices and to analyze what software techniques are required to exploit existing and future accelerators. The candidate will build on an existing multi-core platform based on RISC-V cores and an open-source GPU to develop a full framework and will study which strategies are able to best exploit the available hardware.
Development of multiplexed photon sources for quantum technologies
Quantum information technologies offers several promises in domains such as computation or secured communications. There is a wide variety of technologies available, including photonic qubits. The latter are robust against decoherence and are particularly interesting for quantum communications applications, even at room temperature. They also offers an alternative to other qubits technologies for quantum computing. For the large-scale deployment of those applications, it is necessary to have cheap, compact and scalable devices. To reach this goal, silicon photonics platform is attractive. It allows implementing key components such as generation, manipulation and detection of photonic qubits.
Solid-state photon generation may occur with different physical processes. Among those, the non-linear photon pair generation has several benefits, such as working at room temperature, the ability to generate heralded single photon, or entangled photon pairs…
You will work on multiplexed parametric photon pair sources in order to surpass the inherent limits of the physical process for generating photon pairs. This will include the development, the fabrication monitoring, and the characterization in the laboratory. In the goal of a full integration on chip, it is necessary to be able to filter effectively unwanted light, in order to keep only photons of interest.