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Thesis
Home   /   Thesis   /   Combined Software and Hardware Approaches for Large Scale Sparse Matrix Acceleration

Combined Software and Hardware Approaches for Large Scale Sparse Matrix Acceleration

Electronics and microelectronics - Optoelectronics Engineering sciences New computing paradigms, circuits and technologies, incl. quantum Technological challenges

Abstract

Computational physics, artificial intelligence and graph analytics are important compute problems which depend on processing sparse matrices of huge dimensions. This PhD thesis focuses on the challenges related to efficiently processing such sparse matrices, by applying a systematic software are hardware approach.

Although the processing of sparse matrices has been studied from a purely software perspective for decades, in recent years many dedicated, and very specific hardware, accelerators for sparse data have been proposed. What is missing is a vision of how to properly exploit these accelerators, as well as standard hardware such as GPUs, to efficiently solve a full problem. Prior to solving a matrix problem, it is common to perform pre-processing of the matrix. This can include techniques to improve the numerical stability, to adjust the form of the matrix, and techniques to divide it into smaller sub-matrices (tiling) which can be distributed to processing cores. In the past, this pre-processing has assumed homogenous compute cores. New approaches are needed, to take advantage of heterogeneous cores which can include dedicated accelerators and GPUs. For example, it may make sense to dispatch the sparsest regions to specialized accelerators and to use GPUs for the denser regions, although this has yet to be shown. The purpose of this PhD thesis is to take a broad overview of the processing of sparse matrices and to analyze what software techniques are required to exploit existing and future accelerators. The candidate will build on an existing multi-core platform based on RISC-V cores and an open-source GPU to develop a full framework and will study which strategies are able to best exploit the available hardware.

Laboratory

Département Systèmes et Circuits Intégrés Numériques (LIST)
DSCIN
Laboratoire Systèmes-sur-puce et Technologies Avancées
Université Grenoble Alpes
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