About us
Espace utilisateur
Education
INSTN offers more than 40 diplomas from operator level to post-graduate degree level. 30% of our students are international students.
Professionnal development
Professionnal development
Find a training course
INSTN delivers off-the-self or tailor-made training courses to support the operational excellence of your talents.
Human capital solutions
At INSTN, we are committed to providing our partners with the best human capital solutions to develop and deliver safe & sustainable projects.
Thesis
Home   /   Thesis   /   Development and characterization of embedded memories based on ferroelectric transistors for neuromorphic applications

Development and characterization of embedded memories based on ferroelectric transistors for neuromorphic applications

Artificial intelligence & Data intelligence Electronics and microelectronics - Optoelectronics Engineering sciences Technological challenges

Abstract

As part of CEA-LETI's Devices for Memory and Computation Laboratory (LDMC), you will be working on the development and optimization of FeFET transistors with amorphous oxide semiconductor channels for neuromorphic applications and near-memory computing.
The main challenge when co-integrating semiconductor and ferroelectric oxides is to perfectly assess and control a proper amount of oxygen vacancies, which govern both the ferroelectric properties of HfZrO2 and the conduction properties of semiconducting oxide, and impose major constraints on the manufacturing process steps.
The aim of the proposed internship is to conduct electrical measurements on various kind of elementary devices, stand-alone ferroelectric / semiconductive oxide films up to complete integreted FeFET devices. This will allow to propose an optimized process flow capable to provide both efficient ferroelectric switching performances (speed, low voltage capability…) together with state-of-the-art MOSFET performances (Ion/Ioff, subthreshold slope…).
The student will have access to a large amount of processed 200mm wafers, embedding a large variety of FeFET device flavors with different dimensions. Different process options will be available, either on already-available wafers or on request during the internship. For the latter, this will involve a close interaction with process experts (either deposition, annealing...) for modifying the FeFET process flow.
The student will benefit from state-of-the-art characterization platform, either for material characterization (XPS, UPS, XRD, TEM microscopy…) or for measuring the FeFET electrical performances.

Laboratory

Département Composants Silicium (LETI)
Service des Composants pour le Calcul et la Connectivité
Laboratoire de Composants Mémoires
Aix-Marseille Université
Top envelopegraduation-hatlicensebookuserusersmap-markercalendar-fullbubblecrossmenuarrow-down