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Home   /   Thesis   /   Development of deposit/etch processes for SADP integration to FD10 node

Development of deposit/etch processes for SADP integration to FD10 node

Emerging materials and processes for nanotechnologies and microelectronics Technological challenges


Developement of new technologic nodes involves both a pattern dimension shrink and a pattern density increase. For the last years, development of multi-Patterning strategies with in particular Spacer Patterning (also called SADP) has signifcantly increased. This approach is based on a sacrificial pattern on which a material is depsosited with a conformal configuration to be etched and thus to define spacers used as masks to pattern the sublayer after sacrificial pattern removals. One of the main challenges of this intergration is the material choice in terms of compatibility (thermal budget, selectivity, etc.). Using SiCo(N)-based materials could be a favourable alternative to standard dielectrics (SiO2, SiN). Another challenge is to achieve only one population after SADP : to prevent microloading effects, etching process with an atomic controlwill be developped (ex. pulsing, ALE, etc.). Environmental footprint should be considered during these process developments.
The purpose of this thesis is to set an integration flow with SiCO(N)-based materials, to developp these materials and to determine associated etching strategies.
To lead your research activity, you would be able to benefit privileged environment offered by CEA-Leti with state of the art tool for process development and for material characterization


Département des Plateformes Technologiques (LETI)
Service des procédés de Patterning
Laboratoire Gravure
Université Grenoble Alpes
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