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Thesis
Home   /   Thesis   /   Graph Neural Network-based power prediction of digital architectures

Graph Neural Network-based power prediction of digital architectures

Artificial intelligence & Data intelligence Computer science and software Engineering sciences Technological challenges

Abstract

Performing power analysis is a major step during digital architecture development. This power analysis is needed as soon as the RTL (Register Transfer Level) coding starts, when the most rewarding changes can be made. As designs get larger, power analysis relies on longer simulation traces and becomes almost impossible, as the process generates huge simulation files (> gigabytes or terabytes of data) and long power analysis turnaround times (weeks or even months). Therefore, power models are used to speed up this step. There is a broad range of research on power modeling at RTL, mainly based on analytical or learning-based approaches. Analytical power modeling attempts to correlate application profiles such as memory behavior, branch behavior, and so on with the micro-architecture parameters to create a power model. Whereas, learning-based power modeling generates a model based on the simulation trace of the design and a reference power obtained from sign-off tools. Learning-based power modeling is gaining popularity because it is easier to implement than the analytical approach and does not require in-depth design knowledge. These ML-based methods have shown impressive improvement over analytical methods. However, the classical ML methods (linear regression, neural network, …) are more suitable to generate one model for one given architecture making them difficult to use to generate a generalizable model. Thus, in the last couple of years, a few studies have started to use Graph Neural Networks (GNN) to address model generalization in the field of electronic design automation (EDA). The advantage of a GNN over classical ML approaches is its ability to directly learn from graphs, making it more suitable for EDA problems.
The objective of this PhD is to develop a generalizable model of power consumption of digital electronic architecture, based on GNN. The developed model should be able to estimate, in addition to the average power consumption, the cycle-to-cycle power consumption of any digital electronic architecture. Very few works [1,2] exist in the state of the art on the use of GNNs for power estimation and the models developed in this work are limited to estimating the average power of an architecture. Moreover, several important research questions are not addressed in this work such as the number of data (architectures) needed for the generalization of the model, the impact of the graph structure during training, the selection of architectures used for training and for testing, the choice of features, etc.
Thus, during this PhD, these questions will be studied in order to know their impact during the generation of the model.
The work performed during this PhD thesis will be presented at international conferences and scientific journals. Certain results may be patented.

Laboratory

Département Systèmes et Circuits Intégrés Numériques (LIST)
DSCIN
Laboratoire Environnement de Conception et Architecture
Montpellier
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