Spin qubits in semiconductors quantum dots offer a fast scaling perspective of quantum processors by leveraging the manufacturing techniques of the microelectronics industry. To explore this approach, industrial research teams implemented qubits directly on their existing routes (e.g. FDSOI at CEA-Leti or FinFET at Intel). However, these devices suffer from an important electrostatic disorder stemming from the presence of an Si/SiO2 interface next to the qubits.
An alternative way consists in using semiconductor heterostructures based on Ge/SiGe stacks. They allow the charge confinement between crystalline interfaces, thus drastically reducing the electrostatic disorder. Besides the low effective mass of carriers in Ge allows more relaxed dimensions, while the spin-orbit coupling of holes in Ge allows spin manipulations without integration of any external control element.
The PhD thesis aims at developing a Ge/SiGe-based platform at CEA-Leti. The work will consist in fabricating test structures such as Hall bars on different substrate coupons, perform low temperature characterization and provide feedback to help optimizing the substrates quality. In parallel a 200mm route based on eBeam lithography will be set up for the fabrication of one- and two-dimensional arrays of quantum dots.