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Home   /   Thesis   /   Study and Integration of Monolithic GaN Cascode Transistor

Study and Integration of Monolithic GaN Cascode Transistor


LETI is currently transferring an AlGaN/GaN power electronics technology on 200mm silicon wafers to a renowned industrial partner in the field of power electronics devices (silicon, SiC).

Gallium nitride-based (GaN) power electronics transistors can have either a normally-off (e-mode) or normally-on (d-mode) operation mechanism. For security reasons, there is a preference for e-mode devices. There are three main types of methods to obtain such functionality: either by using a p-type GaN gate, a conduction channel that includes a MOS stack (metal, oxide, semiconductor) or a cascode architecture (by assembling an e-mode and a d-mode device).

The cascode architecture for GaN-based devices is today highly successful as it can be driven with similar strategies than the ones used for more traditional silicon parts and because of its good reliability.

The work of this PhD will consist in conducting a study aiming to optimize the design of the device and identify its key technological steps (epitaxy, deposition, lithography, implantation...) necessary to its fabrication, followed by the coordination of the tasks necessary to its processing in LETI clean rooms. An analysis and interpretation of the obtained electrical measurements will be performed by using finished element simulations (TCAD using Synopsys environment).


Département Composants Silicium (LETI)
Service Intégrations et Technologies pour les conversions d'énergies
Laboratoire des composants de Puissance à Semiconducteur
Université Grenoble Alpes
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