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Fully Depleted Silicon On Insulator Short Design School

Technologies et applications

Technologies et numérique

Nouvelle formation !

En bref

This short course on FD-SOI technology is intended for experienced chip designers, technologists and newcomers to the field. Led by industry experts, it will provide a comprehensive overview of FD-SOI technology and its benefits, addressing multiple aspects of circuit design.

Participants will learn how to efficiently design digital, analog and RF circuits for key application markets. The tutorials will present advanced FD-SOI design techniques and methodologies that drive the development of innovative IP and products across various domains.

A qui s’adresse cette formation ?

This course is primarily aimed at technologists, engineers and scientists who are actively engaged in researching, developing and manufacturing advanced electronic devices. This includes students and professionals from industry and academia who are interested in integrating, fabricating and scaling electronic systems.

These individuals may include:

  • Chip designers involved in the development of low-power, high-performance ICs.
  • Device and process engineers working on advanced node development and integration.
  • R&D scientists exploring next-generation technologies for scalable electronics.
  • Technology managers and system architects may also be interested in gaining seeking a deeper scientific and technical understanding of FD-SOI platforms.

Compétences visées

The central objective of this course is to develop a solid understanding of FD-SOI technology as a foundation for designing innovative semiconductor devices.

Achieving innovation in device design requires careful consideration of the key parameters that can be tuned and optimized. Accordingly, this course offers a comprehensive introduction to FD-SOI technology, addressing its fundamental concepts, device physics, and emerging application domains. It equips students with the essential theoretical background and methodological tools needed to explore new design paradigms, investigate low-power optimization strategies, and contribute to innovation in FD-SOI semiconductor technologies.

This short course, led by industry experts, is designed for chip designers, technologists, and newcomers to FD-SOI platform. Participants will be introduced to the distinctive characteristics of FD-SOI transistors compared with bulk CMOS and will develop the in-depth understanding needed to design accurately and fully leverage the capabilities of this technology. A significant focus will be placed on PDK pathfinding, covering both its content and the methodology behind its development to maximise its effectiveness. The programme will also address eNVM, highlighting its advantages for specialised design strategies and showing how it complements FD-SOI.

 

TRAINING PROGRAM

 

WELCOME AND INTRODUCTION (Day 1 pm)                                                                             

  • Training Schedule                                                                                                            
  • Unlocking Design Potential with FD-SOI: Next Wave in Semiconductor Innovation
  • FAMES project overview and opportunities

FD-SOI : PRINCIPLES AND INNOVATION OPPORTUNITIES (Day 1 pm)                                 

  • From Bulk CMOS to FD-SOI                                                                                
  • Taking advantage of FD-SOI transistor – Advanced RF Design with CMOS FD-SOI: Performance, Efficiency and Design Flexibility
  •  Evolution of technologies from 10nm & 7nm Nodes until the end of Roadmap

USING FD-SOI TO DRIVE ADVANCED CHIP ARCHITECTURE  DEVELOPMENT (Day 2)                                                                                                  

  • FD-SOI design flow for digital circuits design
  • FD-SOI technology: is it a game changer in Power Management Design?
  • Benefits of FD-SOI for the design of oscillators
  • Unlocking RF Design with FD-SOI: Key Advantages and Opportunities

                                                                                                                                                

  • An immersive clean room experience at CEA-Leti

 

  • 10nm FD-SOI Pathfinding DK : From generative methods to technology benchmarking
  • Non-Volatile Memories for Embedded Solutions on 22 nm FD-SOI Node and Beyond
  • FAMES project collaboration opportunities and open access mechanisms

 

  

This course is designed to establish the scientific foundation for the complete design–integration–production chain of FD-SOI devices and related technologies. Participants are expected to have a solid understanding of integrated circuit design fundamentals, including CMOS technology, digital and analog circuit design principles, process design flows, and basic layout techniques. Prior experience with device modelling and simulation tools would be an advantage.

Méthodes et outils pédagogiques


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Contact(s)

INSTN Grenoble

Contact administratif :

Manuela LLORET
manuela.lloret@cea.fr
04 38 78 25 60

Contact pédagogique :

Samir DERROUGH
samir.derrough@cea.fr
+33 4 38 78 20 68

Sessions de formation

Si vous êtes en situation de handicap, veuillez contacter le référent handicap, afin de vérifier les possibilités de mise en oeuvre de l'action de formation, à l'adresse suivante : instn-handicap@cea.fr

Lieu Session
Du 21 septembre 2026
Au 22 septembre 2026
INSTN Grenoble 790,00€ HT S'INSCRIRE

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