As part of the European Chip Act, CEA-Leti is pioneering a new generation of transistors using FDSOI architecture. Our goal is to deliver advanced performance with a strong emphasis on materials and energy efficiency. As we push the limits of planar transistors at 10 nm and 7 nm, we face significant physical challenges, particularly in reducing parasitic elements like capacitance and access resistance, which are critical for minimizing energy loss and optimizing performance. We are eager to tackle these challenges together.
We are excited to offer a unique PhD opportunity for motivated students interested in the field of semiconductor device engineering. Join our team to work on the incorporation and characterization of low-k spacer for advanced 7-10nm FDSOI Technology. This PhD offers the chance to work on a groundbreaking project. If you're curious, innovative, and eager for a challenge, this opportunity is perfect for you!
The impact of the dielectric spacer nature has relevant effects on the overall transistor performances, specifically in non-fully overlapped configuration. The dielectric spacer integration, optimization and engineering remains a challenge and becomes crucial to address technology advancement and scaling down demand. Numerous spacer candidates (SiN, SiCO, SiCON, SiCBN) have been introduced and identified as promising solutions, however, they frequently suffer from inherent defects and adverse electrical characteristics, such as charge trapping and presence of undesired interface states, which hinder their and the overall transistors performance.
Within this framework, the objective of this PhD is to conduct a comprehensive investigation and electrical characterization (CV,IV, BTI, HCI…) of the material spacer (interface, volume), providing an in-depth analysis of transistor performance and its underlying mechanisms. Innovative ultrafast CV stress-measurement characterization on dielectric samples will be also carried out and the correlation between trapping performance and the deposition parameters used in their fabrication will be established. Additionally, the candidate will collaborate closely with experts to contribute to the thin film deposition and characterization of new materials through surface analyses and thin-film characterizations (ellipsometry, FTIR, XRR, XPS…)
Throughout this journey, you will gain a broad spectrum of knowledge, spanning microelectronics materials and processes, analog integrated design, all while addressing the unique challenge of advance 7-10 nm FDSOI technology. You'll collaborate with multidisciplinary teams to develop a deep understanding of FDSOI devices and analyze existing and new measurements. You'll also be part of an integrated multidisciplinary lab, working alongside a team composed of several permanent researchers, exploring a wide range of research applications.