Complementary Field Effect Transistors (CFETs) represent a new generation of vertically stacked CMOS devices, offering a promising path to continue transistor miniaturization and to meet the requirements of high-performance computing.

The objective of this PhD work is to study and optimize the strain engineering of the transistor channel in order to enhance carrier mobility and improve the overall electrical performance of CFET devices. The work will combine numerical modeling of technological processes using finite element methods with experimental characterization of crystalline deformation through transmission electron microscopy coupled with precession electron diffraction (TEM-PED).

The modeling activity will focus on predicting strain distributions and their impact on electrical properties, while accurately accounting for the complexity of the technological stacks and critical fabrication steps such as epitaxy. In parallel, the experimental work will aim to quantify strain fields using TEM-PED and to compare these results with simulation outputs.

This research will contribute to the development of dedicated modeling tools and advanced characterization methodologies adapted to CFET architectures, with the goal of improving spatial resolution, measurement reproducibility, and the overall understanding of strain mechanisms in next-generation transistors.