In our past studies on SiC power devices, the analysis of electrical performances on diodes [1] (idem for future MOSFETs) must take into account the impact of material's defects at the epitaxy and substrate level.
Initially, the thesis work will consist of setting up tools dedicated to our needs in the SiC team. The specifications for these tools have already been established as part of the internship currently underway within the LAPS laboratory. These AI tools will be able to be trained on already existing datasets (SiC diode batches: with electrical data, defect mappings) and complete the previous manually carried out analyses.
In a second phase, the use of the developed tools will be applied to new manufactured and characterized batches. The range of data will then be completed by considering new component architectures (diodes and power MOSFETs), new material characterizations (defects characterization from other tools being installed at Leti, or even with external collaborators: see Line Pilot WBG, see Soitec), new entries (images of defectivity, obtained during the components fabrication in the clean rooms).
Note that the approach applies i) in the case of power to other materials (GaN, diamond, Ga2O3...), ii) also potentially to any component on semiconductor (memory, transistor, photonic, quantum...).