A high resistivity substrate is essential for the design of state-of-the-art high-frequency circuits. The high-resistivity (HR) SOI substrate with a trap-rich layer below the buried oxide (BOX) is the option with the highest performance at present for CMOS technologies. However, these substrates have two major limitations: (1) their relatively high price and (2) the degradation of their RF performance at operating temperatures above 100 °C.
As part of this postdoctoral study, we propose to study, in collaboration with the Catholic University of Louvain (UCL), the RF performance over a wide temperature range of a polycrystalline substrate over its entire thickness (several hundred µm). These polycrystalline substrates indeed have a high density of electronic traps distributed throughout the entire volume, which in principle allows for stable RF performance even at high operating temperatures.
The person hired will participate in the following research: (1) screening of promising substrates from TCAD simulations (e.g. poly-Si, poly-SiC, …), (2) integration of polycrystalline substrates in an SOI process flow at Leti, (3) measurement of RF performances in frequency and temperature at UCL. A particular attention will be placed on understanding the physical phenomena involved through the comparison of experimental and simulation data.