3D integration is currently under great investigation because it offers a solution to keep increasing transistor density while relaxing the constraint on the transistor’s dimension and it eases the co integration of highly heterogeneous technologies compared to a planar scheme.
3D sequential integration offers the possibility of using the third-dimension potential: two stacked layers can be connected at the transistor scale. This contrasts with 3D parallel integration, which is limited to connecting blocks of a few thousand transistors. However, its implementation faces the challenge of being able to process a high performance top transistor at low temperature in order to preserve the bottom FET from any degradation, as the stacked FETs are fabricated sequentially.