Because conventional downsizing based on the empirical Moore's law has reached its limitations, an alternative integration technology, such as three-dimensional integration (3DI) is becoming the mainstream. The 3rd generation of CMOS image sensor (CIS) stacks up to 3 die interconnected by hybrid bonding and High Density Through Silicon Vias (HD-TSVs). Devices and circuits good functioning and integrity have to be maintained in such an integration especially in the close neighborhood of TSVs. Thermal budget, copper pumping, thin wafer warpage can lead to electrical yield and reliability concerns and must be investigated.
The work consists in evaluating the impact of TSV processing and proximity on BEOL and FEOL performance and reliability. Acquired data sets will help to define design rules and in particular a potential Keep-Out Zone (KOZ) and calibrate a finite element model (FFM).