With the advent of nanoelectronics, the reliability of the forthcoming circuits and computation devices is becoming questionable. Indeed, due to huge increases in density integration, lower supply voltages, and variations in the technological process, MOS and emerging nanoelectronic devices will be inherently unreliable. As a consequence, the nanoscale integration of chips built out of unreliable components has emerged as one of the most critical challenges for the next-generation electronic circuit design. To make such nanoscale integration economically viable, new solutions for efficient and fault-tolerant data processing and storage must now be invented.

This post-doctoral position aims at investigating innovative fault-tolerant solutions, at both device- and system-level, that are fundamentally rooted in mathematical models, algorithms, and techniques of information and coding theory. Investigated solutions will build on specific error correcting codes, able to provide reliable error protection even if they themselves operate on unreliable hardware. The goal is to develop the scientific foundation and provide a first proof-of-concept, as an essential condition for bringing about a paradigm shift in the design of future nanoscale circuits.