LETI is a major laboratory in the european microelectronics research, especially in the thin film FDSOI research (Fully Depleted). We propose innovative solutions for the next ITRS roadmap generations (sub 22nm), such as the integration of ultrathin Silicon-Germanium (SiGe) layers in the channel of p type transistors (in order to increase the hole mobility, and to adjust the threshold voltage of pMOSFETs).

The first results show significative gains for hole mobilityy and Vth,p tunning (C. Le Royer et al. ESSDERC 2010, IEDM 2011) but also for basic circuits (L. Hutin et al. IEDM 2010).

In order to further improve the Fully Depleted CMOS DualChannel integration, it is necessary to quantify in details the advantages and the possible drawbacks (form the process and from the electrical performance point of view). LETI wants to compare the two following approaches for SiGe based pMOSFETs (cointegrated with SOI nMOSFETs featuring 6nm body thickness):
.SiGe/SOI hetrostructures ("Localized SiGe epi" on SOI)
.SiGe-On-Insulator ("localized Ge enrichment" on SOI)
Other issues have also to be considered such as the initial substrate (SOI, sSOI) or the Ge content in the SiGe layer…