The candidate will study substrate coupling in millimeter wireless circuit. He will demonstrate the influence of silicon substrate on millimeter circuit design
The first task will consist in establishing the state of the art of substrate reduction technics on millimeter chip. The influence between building blocks at layout level will be analyzed. Parasitic noise effects, frequency and power spurious will be studied with coupling substrate tool. Specifications for layout design in order to reduce spurious will be done, especially for power, analog and digital applications. A design methodology will be proposed with this results.