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Thesis
Home   /   Thesis   /   Junction defect characterization of low therMal Budget SOI MoSFET

Junction defect characterization of low therMal Budget SOI MoSFET

New computing paradigms, circuits and technologies, incl. quantum Technological challenges

Abstract

Join CEA-Leti and CROMA to analyze in depth junctions of a new technology. Indeed, our transistors are fabricated under restricted thermal budget for 3D sequential integration, making dopants activation very challenging! Our team will support you technically and scientifically to conduct this work. Some data are already available and waiting for your analysis.
During this PhD, you will have the opportunity to perform all theses steps:
From the idea (simulation, bibliography, TCAD) 20%
Processes understanding (implantation, SPER) 10%
Integration & cleanroom fabrication management 10%
Characterization (physical & electrical: noise, DLTS…) 50%
Valorization (presentations, article) 10%
This PhD offers a unique chance to be at the forefront of technological innovation and to make a significant impact in the field of advanced SOI. Join us and take the first step towards an exciting career in research and development!

With a background in microelectronics or nanotechnologies, you are curious about integration of new processes, not afraid about equations and liked semiconductors classes at school. You want to solve complex puzzles and enjoy collaborating with others to figure out innovative solutions.

Laboratory

Département Composants Silicium (LETI)
Service des Composants pour le Calcul et la Connectivité
Laboratoire des Transistors Avancés
Université Grenoble Alpes
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