Context : As semiconductor technology scales down to 10 nm and below, Back End of Line (BEOL) scaling presents challenges, particularly in maintaining the integrity of copper interconnects, where line/via resistance and copper fill are key issues. Copper (Cu) interconnections must resist diffusion and delamination while maintaining optimal conductivity. In the traditional Cu damascene process, metal barriers and a Cu seed layer are deposited by PVD to enable electrochemical copper deposition. As dimensions shrink, it becomes increasingly difficult to incorporate tantalum-based diffusion barriers, even with techniques like atomic layer deposition (ALD), as the barrier thickness must be reduced to just a few nanometers. To address this challenge, a self-forming barrier (SFB) process has been proposed. This process uses copper alloys containing elements such as Mn, Ti, Al, and Mg, which segregate at the Cu-dielectric interface, forming an ultra-thin barrier while also serving as a seed layer for electroplating.
Thesis Project: The PhD candidate will join a leading research team to explore and optimize materials for SFBs using Cu alloys. Focus areas include:
- Material Selection & Characterization: develop and analyze Cu alloy thin films by electrochemical and PVD methods to study their microstructure and morphology.
- Barrier Formation: Control alloy migration at the Cu/dielectric interface during thermal annealing and assess barrier effectiveness.
- Electrical & Mechanical Properties: Evaluate SFB impact on electrical resistance, electromigration, and delamination, especially in accelerated tests.
Required skills : Master's degree in electrochemistry or materials science with a strong interest in applied research. A pronounced interest in experimental work, skills in thin film deposition, electrochemistry and materials characterization (AFM, SEM, XPS, XRD, SIMS). You should be able to conduct bibliographic research and organize your work efficiently.
Work Environment: The candidate will work in a renowned laboratory with state-of-the-art 200/300 mm facilities and will participate in the CEA’s NextGen Project on advanced interconnects for high reliability applications.