This short course, led by industry experts, is designed for chip designers, technologists, and newcomers to FD-SOI platform. Participants will be introduced to the distinctive characteristics of FD-SOI transistors compared with bulk CMOS and will develop the in-depth understanding needed to design accurately and fully leverage the capabilities of this technology. A significant focus will be placed on PDK pathfinding, covering both its content and the methodology behind its development to maximise its effectiveness. The programme will also address eNVM, highlighting its advantages for specialised design strategies and showing how it complements FD-SOI.

TRAINING PROGRAM

WELCOME AND INTRODUCTION (Day 1 pm)

• Training Schedule
• Unlocking Design Potential with FD-SOI: Next Wave in Semiconductor Innovation
• FAMES project overview and opportunities

FD-SOI : PRINCIPLES AND INNOVATION OPPORTUNITIES (Day 1 pm)             

• From Bulk CMOS to FD-SOI
• Taking advantage of FD-SOI transistor – Advanced RF Design with CMOS FD-SOI: Performance, Efficiency and Design Flexibility
•  Evolution of technologies from 10nm & 7nm Nodes until the end of Roadmap

USING FD-SOI TO DRIVE ADVANCED CHIP ARCHITECTURE  DEVELOPMENT (Day 2)      

• FD-SOI design flow for digital circuits design
• FD-SOI technology: is it a game changer in Power Management Design?
• Benefits of FD-SOI for the design of oscillators
• Unlocking RF Design with FD-SOI: Key Advantages and Opportunities
• An immersive clean room experience at CEA-Leti

• 10nm FD-SOI Pathfinding DK : From generative methods to technology benchmarking
• Non-Volatile Memories for Embedded Solutions on 22 nm FD-SOI Node and Beyond
• FAMES project collaboration opportunities and open access mechanisms

This course is designed to establish the scientific foundation for the complete design–integration–production chain of FD-SOI devices and related technologies. Participants are expected to have a solid understanding of integrated circuit design fundamentals, including CMOS technology, digital and analog circuit design principles, process design flows, and basic layout techniques. Prior experience with device modelling and simulation tools would be an advantage.